diff --git a/vivado/arty-a7-test-setup/create_project.tcl b/vivado/arty-a7-test-setup/create_project.tcl
index cb6c473..fc2ce57 100644
--- a/vivado/arty-a7-test-setup/create_project.tcl
+++ b/vivado/arty-a7-test-setup/create_project.tcl
@@ -38,7 +38,7 @@ set fileset_design ./../../neorv32/rtl/test_setups/neorv32_test_setup_bootloader
 set fileset_constraints [glob ./*.xdc]
 
 ## Simulation-only sources
-set fileset_sim [list ./../../neorv32/sim/simple/neorv32_tb.simple.vhd ./../../neorv32/sim/simple/uart_rx.simple.vhd]
+set fileset_sim [list ./../../neorv32/sim/neorv32_tb.vhd ./../../neorv32/sim/sim_uart_rx.vhd]
 
 # Add source files
 
diff --git a/vivado/nexys-a7-test-setup/create_project.tcl b/vivado/nexys-a7-test-setup/create_project.tcl
index f1ae4bd..d5b9b1d 100644
--- a/vivado/nexys-a7-test-setup/create_project.tcl
+++ b/vivado/nexys-a7-test-setup/create_project.tcl
@@ -34,7 +34,7 @@ set_property library neorv32 [get_files [glob ./../../neorv32/rtl/core/*.vhd]]
 add_files [glob ./../../neorv32/rtl/test_setups/neorv32_test_setup_bootloader.vhd]
 
 # add source files: simulation-only
-add_files -fileset sim_1 [list ./../../neorv32/sim/simple/neorv32_tb.simple.vhd ./../../neorv32/sim/simple/uart_rx.simple.vhd]
+add_files -fileset sim_1 [list ./../../neorv32/sim/neorv32_tb.vhd ./../../neorv32/sim/sim_uart_rx.vhd]
 
 # add source files: constraints
 add_files -fileset constrs_1 [glob ./*.xdc]