Tang Nano 9K synthesis error

[elialaz]

Hi,

I'm using the Tang Nano 9K setup but seems that there is an error in the project, to be fair I'm using the GOWIN EDA version 1.9.11 because the 1.9.9 is not available anymore.
Here the error log:

GowinSynthesis start Running parser ... ...... Processing 'neorv32_sysinfo(num_harts=1,clock_frequency=27000000,boot_mode_select=0,int_bootloader_en=true,mem_int_imem_en=true,mem_int_imem_rom=false,mem_int_imem_size=16384,mem_int_dmem_en=true,mem_int_dmem_size=8192,icache_en=false,icache_num_blocks=4,icache_block_size=64,dcache_en=false,dcache_num_blocks=4,dcache_block_size=64,xbus_en=false,xbus_cache_en=false,xbus_cache_num_blocks=64,xbus_cache_block_size=32,ocd_en=false,ocd_authentication=false,io_gpio_en=true,io_clint_en=true,io_uart0_en=true,io_uart1_en=false,io_spi_en=false,io_sdi_en=false,io_twi_en=false,io_twd_en=false,io_pwm_en=false,io_wdt_en=false,io_trng_en=false,io_cfs_en=false,io_neoled_en=false,io_gptmr_en=false,io_onewire_en=false,io_dma_en=false,io_slink_en=false,io_crc_en=false)(neorv32_sysinfo_rtl)'("/home/elialaz/Projects/neorv/neorv32-setups/gowineda/tang-nano-9k/test/src/neorv32_sysinfo.vhd":18) ERROR (EX4923) : Expression has 8u elements, expected 6u("/home/elialaz/Projects/neorv/neorv32-setups/gowineda/tang-nano-9k/test/src/neorv32_test_setup_bootloader.vhd":78) ERROR (EX4844) : Netlist 'neorv32_test_setup_bootloader(neorv32_test_setup_bootloader_rtl)' remains a black box due to errors in its contents("/home/elialaz/Projects/neorv/neorv32-setups/gowineda/tang-nano-9k/test/src/neorv32_test_setup_bootloader.vhd":18) GowinSynthesis finish

Thanks in advance!

[stnolting]

I think this is the relevant part:

ERROR (EX4923) : Expression has 8u elements, expected 6u("/home/elialaz/Projects/neorv/neorv32-setups/gowineda/tang-nano-9k/test/src/neorv32_test_setup_bootloader.vhd":78)

Which seems to correspond to this line of code:

https://github.com/stnolting/neorv32/blob/00294c6c29336894f7b105c896e2751cbb204028/rtl/test_setups/neorv32_test_setup_bootloader.vhd#L77-L78

So neorv32_test_setup_bootloader.vhd is you top module, right? Did you make any modifications?

Which processor version are you using?

[elialaz]

@stnolting thanks for the reply :)
I'm using the processor version linked in the repository dependencies. I have not done any modification.

I found out that there are several errors even in the place&route phase.
I already solved all of them but I would like to test if now the design is working properly on the board.

Hopefully I will receive the board in the next weeks and then I will post here the final modification for a working design so if you want you can apply them to this official repo.

[stnolting]

I found out that there are several errors even in the place&route phase.

Could you provide some more information? Were these just issues in the configuration of synthesis?

I will post here the final modification for a working design so if you want you can apply them to this official repo.

That would be great! Thank you very much!

[elialaz]

Could you provide some more information? Were these just issues in the configuration of synthesis?

Yes, the first one posted here is a misconfiguration in the number of GPIO to initiate on the processor.
The other are just misconfiguration of various FPGA pin connection, voltage of operation and bank number in the physical output connection.
I hope the UART is fine and works, if not I will dig deeper because I need the processor work on this board for education purposes.

I will post here when done!

[elialaz]

Hi @stnolting,

Finally I received the board so I manage to check if my modified setup works and seems all fine besides the UART connection. After flashing and connecting to the UART port I cannot manage to get some readable characters, seems that the baud rate is always wrong (I tried every possible frequency) and checking on the internet it seems that is a common issue with this board and the JTAG chip.

I'm a bit lost so if you have suggestions @stnolting it will be very helpful.
Tomorrow maybe I would try to recompile the core with other UART frequency but I'm not sure this would solve the issue with the board.

[stnolting]

Hey @elialaz,

this sounds like a problme with the clock frequency configuration. The UART setup function (by default) gets the time base (i.e. the processor clock frequency) from a memory-mapped register that gets initialized during synthesis from the CLOCK_FREQUENCY generic.

Did you change this generic according to your clock source?

entity neorv32_test_setup_bootloader is
  generic (
    -- adapt these for your setup --
    CLOCK_FREQUENCY   : natural := 100000000; -- clock frequency of clk_i in Hz

The value here must reflect the actual clock freuency of the processor's clk_i signal.

[elialaz]

@stnolting I'm using the test_setup_bootloader.vhd, I checked but the frequency is set to the right value so this shouldn't be the case

entity neorv32_test_setup_bootloader is
  generic (
    -- adapt these for your setup --
    CLOCK_FREQUENCY   : natural := 27000000;  -- clock frequency of clk_i in Hz
    MEM_INT_IMEM_SIZE : natural := 16*1024;   -- size of processor-internal instruction memory in bytes
    MEM_INT_DMEM_SIZE : natural := 8*1024     -- size of processor-internal data memory in bytes
  );

EDIT: i checked even the physical connection but the close should be fine

[stnolting]

Do you get weird UART data or none at all?

You are booting the bootloader, right?

Have you connected an LED to GPIO output 0? Do you see it blinking?

[stnolting]

Do you use a PLL or something inside the FPGA?
27MHz seems like a strange frequency for an external oscillator... 🤔

[elialaz]

@stnolting I get the data and seems all fine but I basically get garbage.

Here the example

elialaz@hps:~/Projects$ tio /dev/ttyUSB1 -b 19200 -d 8 -s 1 -p none -f none
[22:00:34.689] tio v3.7-16-g01e637c
[22:00:34.689] Press ctrl-t q to quit
[22:00:34.699] Connected to /dev/ttyUSB1
�Q���ź�=5��ݚ
            \��X�!QU՞��Q)��Q�8��QY�UϜI$��QY���Q���gE�)QQ�%��)QYQUQњ�})Q)QQQI}�QYQQE�I$8?�|7�\!�u�9�Q����7Qu�%�}3�}��}�s]�1AYQ��Q]�
                                                                                                                                  yx���

Yes the bootloader boots fine and yes the led blinks fine. I think that everything works fine from the neor32 point of view, its just the UART connection or the JTAG chip that as problems.

[elialaz]

Do you use a PLL or something inside the FPGA? 27MHz seems like a strange frequency for an external oscillator... 🤔

No nothing strange, its just the cinese manufacturer's questionable choices for the oscillator chosen

[elialaz]

[elialaz]

I saw that others had this problem and solved by changing the UART to an external converter so maybe it's just this.
In the comments

I have 39 more boards here so maybe tomorrow I will try if it's just this one or is a systemic issue, if you have other ideas feel free to make suggestions and I would try :)

Thanks again for the help @stnolting

[stnolting]

I saw that others had this problem and solved by changing the UART to an external converter so maybe it's just this.

That sounds like a good idea.

Unfortunately, I have never worked with those FPGAs (but I am planning to get one) so I cannot say a thing about the UART-USB bridge... Is there seomthing like an UART reference design by Gowin / Sipeed?

I have 39 more boards

Oh what?! 😅