Merge branch 'main' into slink_dual_irq

README.md

@@ -197,8 +197,7 @@ using Intel Quartus Prime Lite 21.1 (no timing constrains, _balanced optimizatio
 | `rv32i_Zicsr_Zicntr`   | 1578 |  773 | 1024 | 0 | 130 MHz |
 | `rv32imc_Zicsr_Zicntr` | 2338 |  992 | 1024 | 0 | 130 MHz |
 
-> [!TIP]
-> An incremental list of CPU extensions and processor modules can be found in the[Data Sheet: FPGA Implementation Results](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
+An incremental list of CPU extensions and processor modules can be found in the [Data Sheet: FPGA Implementation Results](https://stnolting.github.io/neorv32/#_fpga_implementation_results).
 
 
 ## 4. Performance
@@ -214,8 +213,7 @@ The following table shows the performance results (scores and average CPI) for e
 | _medium_ (`rv32imc_Zicsr_Zifencei`)                      | 62.50 |
 | _performance_ (`rv32imc_Zicsr_Zifencei` + perf. options) | 95.23 |
 
-> [!TIP]
-> More information regarding the CPU performance can be found in the
+More information regarding the CPU performance can be found in the
 [Data Sheet: CPU Performance](https://stnolting.github.io/neorv32/#_cpu_performance).
 The CPU & SoC provide further "tuning" options to optimize the design for maximum performance,
 maximum clock speed, minimal area or minimal power consumption:

rtl/core/neorv32_cpu_control.vhd

@@ -2302,15 +2302,12 @@ begin
   cnt_event(hpmcnt_event_compr_c)    <= '1' when (execute_engine.state = EXECUTE)  and (execute_engine.is_ci = '1')  else '0'; -- executed compressed instruction
   cnt_event(hpmcnt_event_wait_dis_c) <= '1' when (execute_engine.state = DISPATCH) and (issue_engine.valid   = "00") else '0'; -- instruction dispatch wait cycle
   cnt_event(hpmcnt_event_wait_alu_c) <= '1' when (execute_engine.state = ALU_WAIT)                                   else '0'; -- multi-cycle ALU co-processor wait cycle
-
-  cnt_event(hpmcnt_event_branch_c)   <= '1' when (execute_engine.state = BRANCH)   else '0'; -- executed branch instruction
-  cnt_event(hpmcnt_event_branched_c) <= '1' when (execute_engine.state = BRANCHED) else '0'; -- control flow transfer
-
-  cnt_event(hpmcnt_event_load_c)     <= '1' when (ctrl.lsu_req = '1') and (ctrl.lsu_rw = '0')               else '0'; -- executed load operation
-  cnt_event(hpmcnt_event_store_c)    <= '1' when (ctrl.lsu_req = '1') and (ctrl.lsu_rw = '1')               else '0'; -- executed store operation
-  cnt_event(hpmcnt_event_wait_lsu_c) <= '1' when (ctrl.lsu_req = '0') and (execute_engine.state = MEM_WAIT) else '0'; -- load/store unit memory wait cycle
-
-  cnt_event(hpmcnt_event_trap_c)     <= '1' when (trap_ctrl.env_enter = '1') else '0'; -- entered trap
+  cnt_event(hpmcnt_event_branch_c)   <= '1' when (execute_engine.state = BRANCH)                                     else '0'; -- executed branch instruction
+  cnt_event(hpmcnt_event_branched_c) <= '1' when (execute_engine.state = BRANCHED)                                   else '0'; -- control flow transfer
+  cnt_event(hpmcnt_event_load_c)     <= '1' when (ctrl.lsu_req = '1') and (ctrl.lsu_rw = '0')                        else '0'; -- executed load operation
+  cnt_event(hpmcnt_event_store_c)    <= '1' when (ctrl.lsu_req = '1') and (ctrl.lsu_rw = '1')                        else '0'; -- executed store operation
+  cnt_event(hpmcnt_event_wait_lsu_c) <= '1' when (ctrl.lsu_req = '0') and (execute_engine.state = MEM_WAIT)          else '0'; -- load/store unit memory wait cycle
+  cnt_event(hpmcnt_event_trap_c)     <= '1' when (trap_ctrl.env_enter = '1')                                         else '0'; -- entered trap
 
 
 -- ****************************************************************************************************************************

rtl/core/neorv32_fifo.vhd

@@ -73,16 +73,11 @@ architecture neorv32_fifo_rtl of neorv32_fifo is
   signal fifo_mem : fifo_mem_t; -- for fifo_depth_c > 1
   signal fifo_reg : std_ulogic_vector(FIFO_WIDTH-1 downto 0); -- for fifo_depth_c = 1
 
-  -- FIFO control --
-  signal we,    re    : std_ulogic; -- write-/read-enable
-  signal w_pnt, r_pnt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); -- write/read pointer
-  signal w_nxt, r_nxt : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
+  -- Fifo control and status --
+  signal we, re, match, empty, full, half, free, avail : std_ulogic;
 
-  -- read access pointer register for async. read --
-  signal r_pnt_ff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
-
-  -- status --
-  signal match, empty, full, half, free, avail : std_ulogic;
+  -- write/read pointer --
+  signal w_pnt, w_nxt, r_pnt, r_nxt, r_pnt_ff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0); 
 
   -- fill level --
   signal diff : std_ulogic_vector(index_size_f(fifo_depth_c) downto 0);
@@ -97,7 +92,7 @@ begin
 
   -- Pointers -------------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
-  pointer_update: process(rstn_i, clk_i)
+  pointer_reg: process(rstn_i, clk_i)
   begin
     if (rstn_i = '0') then
       w_pnt <= (others => '0');
@@ -106,7 +101,7 @@ begin
       w_pnt <= w_nxt;
       r_pnt <= r_nxt;
     end if;
-  end process pointer_update;
+  end process pointer_reg;
 
   -- async pointer update --
   w_nxt <= (others => '0') when (clear_i = '1') else std_ulogic_vector(unsigned(w_pnt) + 1) when (we = '1') else w_pnt;
@@ -116,7 +111,7 @@ begin
   -- Status ---------------------------------------------------------------------------------
   -- -------------------------------------------------------------------------------------------
 
-  -- more than 1 FIFO entries --
+  -- more than 1 FIFO entry --
   check_large:
   if (fifo_depth_c > 1) generate
     match <= '1' when (r_pnt(r_pnt'left-1 downto 0) = w_pnt(w_pnt'left-1 downto 0)) else '0';
@@ -159,7 +154,7 @@ begin
       end process write_reset_small;
     end generate;
 
-    -- more than 1 FIFO entries --
+    -- more than 1 FIFO entry --
     fifo_write_reset_large:
     if (fifo_depth_c > 1) generate
       write_reset_large: process(rstn_i, clk_i)
@@ -195,7 +190,7 @@ begin
       end process write_small;
     end generate;
 
-    -- more than 1 FIFO entries --
+    -- more than 1 FIFO entry --
     fifo_write_noreset_large:
     if (fifo_depth_c > 1) generate
       write_large: process(clk_i)
@@ -222,7 +217,7 @@ begin
       rdata_o <= fifo_reg;
     end generate;
 
-    -- more than 1 FIFO entries --
+    -- more than 1 FIFO entry --
     fifo_read_async_large:
     if (fifo_depth_c > 1) generate
       async_r_pnt_reg: process(clk_i)
@@ -258,7 +253,7 @@ begin
       end process sync_read_small;
     end generate;
 
-    -- more than 1 FIFO entries --
+    -- more than 1 FIFO entry --
     fifo_read_sync_large:
     if (fifo_depth_c > 1) generate
       sync_read_large: process(clk_i)

rtl/core/neorv32_xbus.vhd

@@ -54,20 +54,20 @@ entity neorv32_xbus is
     ASYNC_TX    : boolean  -- use register buffer for TX data when false
   );
   port (
-    clk_i       : in  std_ulogic; -- global clock line
-    rstn_i      : in  std_ulogic; -- global reset line, low-active
-    bus_req_i   : in  bus_req_t;  -- bus request
-    bus_rsp_o   : out bus_rsp_t;  -- bus response
+    clk_i      : in  std_ulogic; -- global clock line
+    rstn_i     : in  std_ulogic; -- global reset line, low-active
+    bus_req_i  : in  bus_req_t;  -- bus request
+    bus_rsp_o  : out bus_rsp_t;  -- bus response
     --
-    xbus_adr_o  : out std_ulogic_vector(31 downto 0); -- address
-    xbus_dat_i  : in  std_ulogic_vector(31 downto 0); -- read data
-    xbus_dat_o  : out std_ulogic_vector(31 downto 0); -- write data
-    xbus_we_o   : out std_ulogic; -- read/write
-    xbus_sel_o  : out std_ulogic_vector(03 downto 0); -- byte enable
-    xbus_stb_o  : out std_ulogic; -- strobe
-    xbus_cyc_o  : out std_ulogic; -- valid cycle
-    xbus_ack_i  : in  std_ulogic; -- transfer acknowledge
-    xbus_err_i  : in  std_ulogic  -- transfer error
+    xbus_adr_o : out std_ulogic_vector(31 downto 0); -- address
+    xbus_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
+    xbus_dat_o : out std_ulogic_vector(31 downto 0); -- write data
+    xbus_we_o  : out std_ulogic; -- read/write
+    xbus_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
+    xbus_stb_o : out std_ulogic; -- strobe
+    xbus_cyc_o : out std_ulogic; -- valid cycle
+    xbus_ack_i : in  std_ulogic; -- transfer acknowledge
+    xbus_err_i : in  std_ulogic  -- transfer error
   );
 end neorv32_xbus;