diff --git a/sw/common/crt0.S b/sw/common/crt0.S
index 0f0a156a1..440338a33 100644
--- a/sw/common/crt0.S
+++ b/sw/common/crt0.S
@@ -72,21 +72,21 @@ __crt0_entry:
 
 
 // ************************************************************************************************
-// Dual-core setup - wait for configuration if we are not core 0.
+// SMP multi-core setup - wait for configuration if we are not core 0.
 // ************************************************************************************************
-#ifndef DISABLE_DUALCORE
-__crt0_dualcore_check:
-  beqz  x1, __crt0_dualcore_primary         // proceed with normal boot-up if we are core 0
+#ifndef DISABLE_MULTICORE
+__crt0_multicore_check:
+  beqz  x1, __crt0_multicore_primary        // proceed with normal boot-up if we are core 0
 
   // setup machine software interrupt
-  la    x15, __crt0_dualcore_wakeup
+  la    x15, __crt0_multicore_wakeup
   csrw  mtvec, x15                          // install interrupt handler
   csrsi mie, 1 << 3                         // enable software interrupt source
   csrsi mstatus, 1 << 3                     // enable machine-level interrupts
   j     __crt0_sleep                        // wait for interrupt in sleep mode
 
   // machine software interrupt handler
-__crt0_dualcore_wakeup:
+__crt0_multicore_wakeup:
   li    x14,  0xfff40000                    // CLINT.MSWI base address
   slli  x15,  x1, 2                         // offset = hart_id * 4
   add   x14,  x14, x15
@@ -94,23 +94,23 @@ __crt0_dualcore_wakeup:
 
   csrr  x14, mcause
   li    x15, 0x80000003                     // is machine software interrupt?
-  bne   x14, x15, __crt0_dualcore_exit      // go back to sleep if not
+  bne   x14, x15, __crt0_multicore_exit     // go back to sleep if not
 
   // get launch configuration from core 0
   csrw  0xbc2, zero                         // ICC.SR: link select = 0
   csrr  x13, 0xbc0                          // ICC.RX: signature
   li    x14, 0xffab4321                     // expected signature
-  bne   x14, x13, __crt0_dualcore_exit      // abort if incorrect signature
+  bne   x14, x13, __crt0_multicore_exit     // abort if incorrect signature
 
   csrw  0xbc1, x14                          // ICC.TX: acknowledge start
   csrr  x2,  0xbc0                          // ICC.RX: stack_top -> sp
   csrr  x12, 0xbc0                          // ICC.RX: entry_point
   j     __crt0_main_entry                   // start main function
 
-__crt0_dualcore_exit:
+__crt0_multicore_exit:
   mret                                      // go back to sleep
 
-__crt0_dualcore_primary:
+__crt0_multicore_primary:
 #endif
 
 
diff --git a/sw/lib/source/neorv32_smp.c b/sw/lib/source/neorv32_smp.c
index da5797492..882a46d00 100644
--- a/sw/lib/source/neorv32_smp.c
+++ b/sw/lib/source/neorv32_smp.c
@@ -27,7 +27,7 @@
  **************************************************************************/
 int neorv32_smp_launch(int hart_id, void (*entry_point)(void), uint8_t* stack_memory, size_t stack_size_bytes) {
 
-  const uint32_t signature = 0xffab4321u;
+  const uint32_t magic_number = 0xffab4321u;
   int num_cores = (int)NEORV32_SYSINFO->MISC[SYSINFO_MISC_HART];
 
   // sanity checks
@@ -47,7 +47,7 @@ int neorv32_smp_launch(int hart_id, void (*entry_point)(void), uint8_t* stack_me
   uint32_t stack_top = ((uint32_t)stack_memory + (uint32_t)(stack_size_bytes-1)) & 0xfffffff0u;
 
   // send launch configuration
-  neorv32_smp_icc_put(hart_id, signature); // signature
+  neorv32_smp_icc_put(hart_id, magic_number); // identifies valid configuration
   neorv32_smp_icc_put(hart_id, stack_top); // top of core's stack
   neorv32_smp_icc_put(hart_id, (uint32_t)entry_point); // entry point
 
@@ -58,11 +58,11 @@ int neorv32_smp_launch(int hart_id, void (*entry_point)(void), uint8_t* stack_me
   int cnt = 0;
   while (1) {
     if (neorv32_smp_icc_avail(hart_id)) {
-      if (neorv32_smp_icc_get(hart_id) == signature) {
+      if (neorv32_smp_icc_get(hart_id) == magic_number) {
         return 0;
       }
     }
-    if (cnt > 10000) {
+    if (cnt > 1000) {
       return -2; // timeout; core did not respond
     }
     cnt++;