From 1b0118dab629249b404534a7d9ed93f70ba6c68a Mon Sep 17 00:00:00 2001
From: Yen-Fu Chen <qwe661234@gmail.com>
Date: Fri, 15 Dec 2023 20:01:17 +0800
Subject: [PATCH] Fix constant optimization on RV32F instructions

Because some RV32F instructions use the interger register, we need to
handle these instructions in constant optimization.

Close: #258
---
 src/rv32_constopt.c | 35 ++++++++++++++++++++++++++++-------
 1 file changed, 28 insertions(+), 7 deletions(-)

diff --git a/src/rv32_constopt.c b/src/rv32_constopt.c
index bccdd1072..f1d2321b7 100644
--- a/src/rv32_constopt.c
+++ b/src/rv32_constopt.c
@@ -650,29 +650,50 @@ CONSTOPT(fmaxs, {})
  */
 
 /* FCVT.W.S */
-CONSTOPT(fcvtws, {})
+CONSTOPT(fcvtws, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FCVT.WU.S */
-CONSTOPT(fcvtwus, {})
+CONSTOPT(fcvtwus, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FMV.X.W */
-CONSTOPT(fmvxw, {})
+CONSTOPT(fmvxw, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FEQ.S performs a quiet comparison: it only sets the invalid operation
  * exception flag if either input is a signaling NaN.
  */
-CONSTOPT(feqs, {})
+CONSTOPT(feqs, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FLT.S and FLE.S perform what the IEEE 754-2008 standard refers to as
  * signaling comparisons: that is, they set the invalid operation exception
  * flag if either input is NaN.
  */
-CONSTOPT(flts, {})
+CONSTOPT(flts, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
-CONSTOPT(fles, {})
+CONSTOPT(fles, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FCLASS.S */
-CONSTOPT(fclasss, {})
+CONSTOPT(fclasss, {
+    if (ir->rd)
+        info->is_constant[ir->rd] = false;
+})
 
 /* FCVT.S.W */
 CONSTOPT(fcvtsw, {})