From 0799bcfc4a80d05335e729cfd6830fb30440a96e Mon Sep 17 00:00:00 2001 From: teobiton Date: Sat, 27 Jan 2024 18:21:23 +0100 Subject: [PATCH] Fix top testbench VERILOG_SOURCES --- tb/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tb/Makefile b/tb/Makefile index 696f247..ee124ba 100644 --- a/tb/Makefile +++ b/tb/Makefile @@ -23,7 +23,7 @@ CORE_DIRECTORY = $(HW_DIRECTORY)/$(TOPLEVEL) CORE_SOURCES := $(shell cat $(CORE_DIRECTORY)/Flist.$(TOPLEVEL)) # Pointing to the verilog files to test -VERILOG_SOURCES = $(addprefix $(ROOT_DIRECTORY)/, $(CORE_SOURCES)) $(ITF_DIRECTORY)/simple_reg_interface.sv +VERILOG_SOURCES = $(addprefix $(ROOT_DIRECTORY)/, $(CORE_SOURCES)) # Verilator extra arguments to build waves EXTRA_ARGS += --trace --trace-structs --trace-fst