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board-ardbeg-memory.c
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/*
* Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
* 02111-1307, USA
*/
typedef unsigned int u8;
typedef unsigned int u32;
#define TEGRA12_MAX_TABLE_ID_LEN 60
#define TEGRA12_EMC_MAX_NUM_REGS 200
#define TEGRA12_EMC_MAX_NUM_BURST_REGS 175
#define TEGRA12_EMC_MAX_UP_DOWN_REGS 40
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
struct tegra12_emc_table {
u8 rev;
char table_id[TEGRA12_MAX_TABLE_ID_LEN];
unsigned long rate;
int emc_min_mv;
int gk20a_min_mv;
char src_name[16];
u32 src_sel_reg;
int burst_regs_num;
int burst_up_down_regs_num;
/* unconditionally updated in one burst shot */
u32 burst_regs[TEGRA12_EMC_MAX_NUM_BURST_REGS];
/* one burst shot, but update time depends on rate change direction */
u32 burst_up_down_regs[TEGRA12_EMC_MAX_UP_DOWN_REGS];
/* updated separately under some conditions */
u32 emc_zcal_cnt_long;
u32 emc_acal_interval;
u32 emc_ctt_term_ctrl;
u32 emc_cfg;
u32 emc_cfg_2;
u32 emc_sel_dpd_ctrl;
u32 emc_cfg_dig_dll;
u32 emc_bgbias_ctl0;
u32 emc_auto_cal_config2;
u32 emc_auto_cal_config3;
u32 emc_auto_cal_config;
u32 emc_mode_reset;
u32 emc_mode_1;
u32 emc_mode_2;
u32 emc_mode_4;
u32 clock_change_latency;
};
struct tegra12_emc_pdata {
const char *description;
int num_tables;
struct tegra12_emc_table *tables;
};
static struct tegra12_emc_table ardbeg_ddr3_emc_table_pm358[] = {
{
0x18, /* V5.0.12 */
"03_12750_02_V5.0.12_V0.9", /* DVFS table version */
12750, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
"pllp_out0", /* clock source id */
0x4000003e, /* CLK_SOURCE_EMC */
164, /* number of burst_regs */
31, /* number of up_down_regs */
{
0x00000000, /* EMC_RC */
0x00000003, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000000, /* EMC_RAS */
0x00000000, /* EMC_RP */
0x00000004, /* EMC_R2W */
0x0000000a, /* EMC_W2R */
0x00000003, /* EMC_R2P */
0x0000000b, /* EMC_W2P */
0x00000000, /* EMC_RD_RCD */
0x00000000, /* EMC_WR_RCD */
0x00000003, /* EMC_RRD */
0x00000003, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x00000006, /* EMC_WDV_MASK */
0x00000006, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
0x00000005, /* EMC_EINPUT */
0x00000005, /* EMC_EINPUT_DURATION */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000004, /* EMC_QRST */
0x0000000c, /* EMC_QSAFE */
0x0000000d, /* EMC_RDV */
0x0000000f, /* EMC_RDV_MASK */
0x00000060, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000018, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x00000007, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
0x00000005, /* EMC_TXSR */
0x00000005, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
0x00000000, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
0x00000064, /* EMC_TREFBW */
0x00000000, /* EMC_FBIO_CFG6 */
0x00000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
0x00064000, /* EMC_DLL_XFORM_DQS4 */
0x00064000, /* EMC_DLL_XFORM_DQS5 */
0x00064000, /* EMC_DLL_XFORM_DQS6 */
0x00064000, /* EMC_DLL_XFORM_DQS7 */
0x00064000, /* EMC_DLL_XFORM_DQS8 */
0x00064000, /* EMC_DLL_XFORM_DQS9 */
0x00064000, /* EMC_DLL_XFORM_DQS10 */
0x00064000, /* EMC_DLL_XFORM_DQS11 */
0x00064000, /* EMC_DLL_XFORM_DQS12 */
0x00064000, /* EMC_DLL_XFORM_DQS13 */
0x00064000, /* EMC_DLL_XFORM_DQS14 */
0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
0x00000000, /* EMC_DLL_XFORM_QUSE3 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
0x00000000, /* EMC_DLL_XFORM_ADDR3 */
0x00000000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
0x00000000, /* EMC_DLL_XFORM_QUSE11 */
0x00000000, /* EMC_DLL_XFORM_QUSE12 */
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000, /* EMC_DLL_XFORM_DQ0 */
0x000fc000, /* EMC_DLL_XFORM_DQ1 */
0x000fc000, /* EMC_DLL_XFORM_DQ2 */
0x000fc000, /* EMC_DLL_XFORM_DQ3 */
0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
0x0130b118, /* EMC_XM2DQSPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
0x51451400, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
0x51451400, /* EMC_XM2DQSPADCTRL6 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
0x00000007, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
0x00000000, /* EMC_ZCAL_INTERVAL */
0x00000042, /* EMC_ZCAL_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x0000f2f3, /* EMC_CFG_PIPE */
0x800001c5, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* EMC_QPOP */
0x40040001, /* MC_EMEM_ARB_CFG */
0x8000000a, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
0x00000002, /* MC_EMEM_ARB_TIMING_RC */
0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
0x77e30303, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
0x00000007, /* MC_PTSA_GRANT_DECREMENT */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73240000, /* EMC_CFG */
0x000008c5, /* EMC_CFG_2 */
0x00040128, /* EMC_SEL_DPD_CTRL */
0x002c0068, /* EMC_CFG_DIG_DLL */
0x00000008, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
0x18, /* V5.0.12 */
"03_20400_02_V5.0.12_V0.9", /* DVFS table version */
20400, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
"pllp_out0", /* clock source id */
0x40000026, /* CLK_SOURCE_EMC */
164, /* number of burst_regs */
31, /* number of up_down_regs */
{
0x00000000, /* EMC_RC */
0x00000005, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000000, /* EMC_RAS */
0x00000000, /* EMC_RP */
0x00000004, /* EMC_R2W */
0x0000000a, /* EMC_W2R */
0x00000003, /* EMC_R2P */
0x0000000b, /* EMC_W2P */
0x00000000, /* EMC_RD_RCD */
0x00000000, /* EMC_WR_RCD */
0x00000003, /* EMC_RRD */
0x00000003, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x00000006, /* EMC_WDV_MASK */
0x00000006, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
0x00000005, /* EMC_EINPUT */
0x00000005, /* EMC_EINPUT_DURATION */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000004, /* EMC_QRST */
0x0000000c, /* EMC_QSAFE */
0x0000000d, /* EMC_RDV */
0x0000000f, /* EMC_RDV_MASK */
0x0000009a, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000026, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x00000007, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
0x00000006, /* EMC_TXSR */
0x00000006, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
0x00000000, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
0x000000a0, /* EMC_TREFBW */
0x00000000, /* EMC_FBIO_CFG6 */
0x00000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
0x00064000, /* EMC_DLL_XFORM_DQS4 */
0x00064000, /* EMC_DLL_XFORM_DQS5 */
0x00064000, /* EMC_DLL_XFORM_DQS6 */
0x00064000, /* EMC_DLL_XFORM_DQS7 */
0x00064000, /* EMC_DLL_XFORM_DQS8 */
0x00064000, /* EMC_DLL_XFORM_DQS9 */
0x00064000, /* EMC_DLL_XFORM_DQS10 */
0x00064000, /* EMC_DLL_XFORM_DQS11 */
0x00064000, /* EMC_DLL_XFORM_DQS12 */
0x00064000, /* EMC_DLL_XFORM_DQS13 */
0x00064000, /* EMC_DLL_XFORM_DQS14 */
0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
0x00000000, /* EMC_DLL_XFORM_QUSE3 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
0x00000000, /* EMC_DLL_XFORM_ADDR3 */
0x00000000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
0x00000000, /* EMC_DLL_XFORM_QUSE11 */
0x00000000, /* EMC_DLL_XFORM_QUSE12 */
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000, /* EMC_DLL_XFORM_DQ0 */
0x000fc000, /* EMC_DLL_XFORM_DQ1 */
0x000fc000, /* EMC_DLL_XFORM_DQ2 */
0x000fc000, /* EMC_DLL_XFORM_DQ3 */
0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
0x0130b118, /* EMC_XM2DQSPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
0x51451400, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
0x51451400, /* EMC_XM2DQSPADCTRL6 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
0x0000000b, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
0x00000000, /* EMC_ZCAL_INTERVAL */
0x00000042, /* EMC_ZCAL_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x0000f2f3, /* EMC_CFG_PIPE */
0x8000023a, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* EMC_QPOP */
0x40020001, /* MC_EMEM_ARB_CFG */
0x80000012, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
0x00000002, /* MC_EMEM_ARB_TIMING_RC */
0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
0x76230303, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
0x0000000a, /* MC_PTSA_GRANT_DECREMENT */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73240000, /* EMC_CFG */
0x000008c5, /* EMC_CFG_2 */
0x00040128, /* EMC_SEL_DPD_CTRL */
0x002c0068, /* EMC_CFG_DIG_DLL */
0x00000008, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
0x18, /* V5.0.12 */
"03_40800_02_V5.0.12_V0.9", /* DVFS table version */
40800, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
"pllp_out0", /* clock source id */
0x40000012, /* CLK_SOURCE_EMC */
164, /* number of burst_regs */
31, /* number of up_down_regs */
{
0x00000001, /* EMC_RC */
0x0000000a, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000001, /* EMC_RAS */
0x00000000, /* EMC_RP */
0x00000004, /* EMC_R2W */
0x0000000a, /* EMC_W2R */
0x00000003, /* EMC_R2P */
0x0000000b, /* EMC_W2P */
0x00000000, /* EMC_RD_RCD */
0x00000000, /* EMC_WR_RCD */
0x00000003, /* EMC_RRD */
0x00000003, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x00000006, /* EMC_WDV_MASK */
0x00000006, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
0x00000005, /* EMC_EINPUT */
0x00000005, /* EMC_EINPUT_DURATION */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000004, /* EMC_QRST */
0x0000000c, /* EMC_QSAFE */
0x0000000d, /* EMC_RDV */
0x0000000f, /* EMC_RDV_MASK */
0x00000134, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x0000004d, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x00000008, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
0x0000000c, /* EMC_TXSR */
0x0000000c, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
0x00000000, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
0x0000013f, /* EMC_TREFBW */
0x00000000, /* EMC_FBIO_CFG6 */
0x00000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
0x00064000, /* EMC_DLL_XFORM_DQS4 */
0x00064000, /* EMC_DLL_XFORM_DQS5 */
0x00064000, /* EMC_DLL_XFORM_DQS6 */
0x00064000, /* EMC_DLL_XFORM_DQS7 */
0x00064000, /* EMC_DLL_XFORM_DQS8 */
0x00064000, /* EMC_DLL_XFORM_DQS9 */
0x00064000, /* EMC_DLL_XFORM_DQS10 */
0x00064000, /* EMC_DLL_XFORM_DQS11 */
0x00064000, /* EMC_DLL_XFORM_DQS12 */
0x00064000, /* EMC_DLL_XFORM_DQS13 */
0x00064000, /* EMC_DLL_XFORM_DQS14 */
0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
0x00000000, /* EMC_DLL_XFORM_QUSE3 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
0x00000000, /* EMC_DLL_XFORM_ADDR3 */
0x00000000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
0x00000000, /* EMC_DLL_XFORM_QUSE11 */
0x00000000, /* EMC_DLL_XFORM_QUSE12 */
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000, /* EMC_DLL_XFORM_DQ0 */
0x000fc000, /* EMC_DLL_XFORM_DQ1 */
0x000fc000, /* EMC_DLL_XFORM_DQ2 */
0x000fc000, /* EMC_DLL_XFORM_DQ3 */
0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
0x0130b118, /* EMC_XM2DQSPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
0x51451400, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
0x51451400, /* EMC_XM2DQSPADCTRL6 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
0x00000015, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
0x00000000, /* EMC_ZCAL_INTERVAL */
0x00000042, /* EMC_ZCAL_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x0000f2f3, /* EMC_CFG_PIPE */
0x80000370, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* EMC_QPOP */
0xa0000001, /* MC_EMEM_ARB_CFG */
0x80000017, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
0x00000002, /* MC_EMEM_ARB_TIMING_RC */
0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
0x74a30303, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
0x00000014, /* MC_PTSA_GRANT_DECREMENT */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
0x00ff0049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73240000, /* EMC_CFG */
0x000008c5, /* EMC_CFG_2 */
0x00040128, /* EMC_SEL_DPD_CTRL */
0x002c0068, /* EMC_CFG_DIG_DLL */
0x00000008, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
0x18, /* V5.0.12 */
"03_68000_02_V5.0.12_V0.9", /* DVFS table version */
68000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
"pllp_out0", /* clock source id */
0x4000000a, /* CLK_SOURCE_EMC */
164, /* number of burst_regs */
31, /* number of up_down_regs */
{
0x00000003, /* EMC_RC */
0x00000011, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000002, /* EMC_RAS */
0x00000000, /* EMC_RP */
0x00000004, /* EMC_R2W */
0x0000000a, /* EMC_W2R */
0x00000003, /* EMC_R2P */
0x0000000b, /* EMC_W2P */
0x00000000, /* EMC_RD_RCD */
0x00000000, /* EMC_WR_RCD */
0x00000003, /* EMC_RRD */
0x00000003, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x00000006, /* EMC_WDV_MASK */
0x00000006, /* EMC_QUSE */
0x00000002, /* EMC_QUSE_WIDTH */
0x00000000, /* EMC_IBDLY */
0x00000005, /* EMC_EINPUT */
0x00000005, /* EMC_EINPUT_DURATION */
0x00010000, /* EMC_PUTERM_EXTRA */
0x00000003, /* EMC_PUTERM_WIDTH */
0x00000000, /* EMC_PUTERM_ADJ */
0x00000000, /* EMC_CDB_CNTL_1 */
0x00000000, /* EMC_CDB_CNTL_2 */
0x00000000, /* EMC_CDB_CNTL_3 */
0x00000004, /* EMC_QRST */
0x0000000c, /* EMC_QSAFE */
0x0000000d, /* EMC_RDV */
0x0000000f, /* EMC_RDV_MASK */
0x00000202, /* EMC_REFRESH */
0x00000000, /* EMC_BURST_REFRESH_NUM */
0x00000080, /* EMC_PRE_REFRESH_REQ_CNT */
0x00000002, /* EMC_PDEX2WR */
0x00000002, /* EMC_PDEX2RD */
0x00000001, /* EMC_PCHG2PDEN */
0x00000000, /* EMC_ACT2PDEN */
0x0000000f, /* EMC_AR2PDEN */
0x0000000f, /* EMC_RW2PDEN */
0x00000013, /* EMC_TXSR */
0x00000013, /* EMC_TXSRDLL */
0x00000004, /* EMC_TCKE */
0x00000005, /* EMC_TCKESR */
0x00000004, /* EMC_TPD */
0x00000001, /* EMC_TFAW */
0x00000000, /* EMC_TRPAB */
0x00000005, /* EMC_TCLKSTABLE */
0x00000005, /* EMC_TCLKSTOP */
0x00000213, /* EMC_TREFBW */
0x00000000, /* EMC_FBIO_CFG6 */
0x00000000, /* EMC_ODT_WRITE */
0x00000000, /* EMC_ODT_READ */
0x106aa298, /* EMC_FBIO_CFG5 */
0x002c00a0, /* EMC_CFG_DIG_DLL */
0x00008000, /* EMC_CFG_DIG_DLL_PERIOD */
0x00064000, /* EMC_DLL_XFORM_DQS0 */
0x00064000, /* EMC_DLL_XFORM_DQS1 */
0x00064000, /* EMC_DLL_XFORM_DQS2 */
0x00064000, /* EMC_DLL_XFORM_DQS3 */
0x00064000, /* EMC_DLL_XFORM_DQS4 */
0x00064000, /* EMC_DLL_XFORM_DQS5 */
0x00064000, /* EMC_DLL_XFORM_DQS6 */
0x00064000, /* EMC_DLL_XFORM_DQS7 */
0x00064000, /* EMC_DLL_XFORM_DQS8 */
0x00064000, /* EMC_DLL_XFORM_DQS9 */
0x00064000, /* EMC_DLL_XFORM_DQS10 */
0x00064000, /* EMC_DLL_XFORM_DQS11 */
0x00064000, /* EMC_DLL_XFORM_DQS12 */
0x00064000, /* EMC_DLL_XFORM_DQS13 */
0x00064000, /* EMC_DLL_XFORM_DQS14 */
0x00064000, /* EMC_DLL_XFORM_DQS15 */
0x00000000, /* EMC_DLL_XFORM_QUSE0 */
0x00000000, /* EMC_DLL_XFORM_QUSE1 */
0x00000000, /* EMC_DLL_XFORM_QUSE2 */
0x00000000, /* EMC_DLL_XFORM_QUSE3 */
0x00000000, /* EMC_DLL_XFORM_QUSE4 */
0x00000000, /* EMC_DLL_XFORM_QUSE5 */
0x00000000, /* EMC_DLL_XFORM_QUSE6 */
0x00000000, /* EMC_DLL_XFORM_QUSE7 */
0x00000000, /* EMC_DLL_XFORM_ADDR0 */
0x00000000, /* EMC_DLL_XFORM_ADDR1 */
0x00000000, /* EMC_DLL_XFORM_ADDR2 */
0x00000000, /* EMC_DLL_XFORM_ADDR3 */
0x00000000, /* EMC_DLL_XFORM_ADDR4 */
0x00000000, /* EMC_DLL_XFORM_ADDR5 */
0x00000000, /* EMC_DLL_XFORM_QUSE8 */
0x00000000, /* EMC_DLL_XFORM_QUSE9 */
0x00000000, /* EMC_DLL_XFORM_QUSE10 */
0x00000000, /* EMC_DLL_XFORM_QUSE11 */
0x00000000, /* EMC_DLL_XFORM_QUSE12 */
0x00000000, /* EMC_DLL_XFORM_QUSE13 */
0x00000000, /* EMC_DLL_XFORM_QUSE14 */
0x00000000, /* EMC_DLL_XFORM_QUSE15 */
0x00000000, /* EMC_DLI_TRIM_TXDQS0 */
0x00000000, /* EMC_DLI_TRIM_TXDQS1 */
0x00000000, /* EMC_DLI_TRIM_TXDQS2 */
0x00000000, /* EMC_DLI_TRIM_TXDQS3 */
0x00000000, /* EMC_DLI_TRIM_TXDQS4 */
0x00000000, /* EMC_DLI_TRIM_TXDQS5 */
0x00000000, /* EMC_DLI_TRIM_TXDQS6 */
0x00000000, /* EMC_DLI_TRIM_TXDQS7 */
0x00000000, /* EMC_DLI_TRIM_TXDQS8 */
0x00000000, /* EMC_DLI_TRIM_TXDQS9 */
0x00000000, /* EMC_DLI_TRIM_TXDQS10 */
0x00000000, /* EMC_DLI_TRIM_TXDQS11 */
0x00000000, /* EMC_DLI_TRIM_TXDQS12 */
0x00000000, /* EMC_DLI_TRIM_TXDQS13 */
0x00000000, /* EMC_DLI_TRIM_TXDQS14 */
0x00000000, /* EMC_DLI_TRIM_TXDQS15 */
0x000fc000, /* EMC_DLL_XFORM_DQ0 */
0x000fc000, /* EMC_DLL_XFORM_DQ1 */
0x000fc000, /* EMC_DLL_XFORM_DQ2 */
0x000fc000, /* EMC_DLL_XFORM_DQ3 */
0x0000fc00, /* EMC_DLL_XFORM_DQ4 */
0x0000fc00, /* EMC_DLL_XFORM_DQ5 */
0x0000fc00, /* EMC_DLL_XFORM_DQ6 */
0x0000fc00, /* EMC_DLL_XFORM_DQ7 */
0x10000280, /* EMC_XM2CMDPADCTRL */
0x00000000, /* EMC_XM2CMDPADCTRL4 */
0x00111111, /* EMC_XM2CMDPADCTRL5 */
0x0130b118, /* EMC_XM2DQSPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL2 */
0x00000000, /* EMC_XM2DQPADCTRL3 */
0x77ffc081, /* EMC_XM2CLKPADCTRL */
0x00000e0e, /* EMC_XM2CLKPADCTRL2 */
0x81f1f108, /* EMC_XM2COMPPADCTRL */
0x07070004, /* EMC_XM2VTTGENPADCTRL */
0x0000003f, /* EMC_XM2VTTGENPADCTRL2 */
0x016eeeee, /* EMC_XM2VTTGENPADCTRL3 */
0x51451400, /* EMC_XM2DQSPADCTRL3 */
0x00514514, /* EMC_XM2DQSPADCTRL4 */
0x00514514, /* EMC_XM2DQSPADCTRL5 */
0x51451400, /* EMC_XM2DQSPADCTRL6 */
0x0000003f, /* EMC_DSR_VTTGEN_DRV */
0x00000022, /* EMC_TXDSRVTTGEN */
0x00000000, /* EMC_FBIO_SPARE */
0x00000000, /* EMC_ZCAL_INTERVAL */
0x00000042, /* EMC_ZCAL_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT */
0x000e000e, /* EMC_MRS_WAIT_CNT2 */
0x00000000, /* EMC_CTT */
0x00000003, /* EMC_CTT_DURATION */
0x0000f2f3, /* EMC_CFG_PIPE */
0x8000050e, /* EMC_DYN_SELF_REF_CONTROL */
0x0000000a, /* EMC_QPOP */
0x00000001, /* MC_EMEM_ARB_CFG */
0x8000001e, /* MC_EMEM_ARB_OUTSTANDING_REQ */
0x00000001, /* MC_EMEM_ARB_TIMING_RCD */
0x00000001, /* MC_EMEM_ARB_TIMING_RP */
0x00000002, /* MC_EMEM_ARB_TIMING_RC */
0x00000000, /* MC_EMEM_ARB_TIMING_RAS */
0x00000002, /* MC_EMEM_ARB_TIMING_FAW */
0x00000001, /* MC_EMEM_ARB_TIMING_RRD */
0x00000002, /* MC_EMEM_ARB_TIMING_RAP2PRE */
0x00000008, /* MC_EMEM_ARB_TIMING_WAP2PRE */
0x00000003, /* MC_EMEM_ARB_TIMING_R2R */
0x00000002, /* MC_EMEM_ARB_TIMING_W2W */
0x00000003, /* MC_EMEM_ARB_TIMING_R2W */
0x00000006, /* MC_EMEM_ARB_TIMING_W2R */
0x06030203, /* MC_EMEM_ARB_DA_TURNS */
0x000a0402, /* MC_EMEM_ARB_DA_COVERS */
0x74230403, /* MC_EMEM_ARB_MISC0 */
0x001f0000, /* MC_EMEM_ARB_RING1_THROTTLE */
},
{
0x00000001, /* MC_MLL_MPCORER_PTSA_RATE */
0x00000021, /* MC_PTSA_GRANT_DECREMENT */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_XUSB_1 */
0x00ff00b0, /* MC_LATENCY_ALLOWANCE_TSEC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMCA_0 */
0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SDMMC_0 */
0x00ff00ec, /* MC_LATENCY_ALLOWANCE_SDMMCAB_0 */
0x00e90049, /* MC_LATENCY_ALLOWANCE_PPCS_0 */
0x00ff0080, /* MC_LATENCY_ALLOWANCE_PPCS_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORE_0 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_MPCORELP_0 */
0x000800ff, /* MC_LATENCY_ALLOWANCE_HC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_HC_1 */
0x00ff0004, /* MC_LATENCY_ALLOWANCE_AVPC_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_GPU_0 */
0x00ff00a3, /* MC_LATENCY_ALLOWANCE_MSENC_0 */
0x00ff0024, /* MC_LATENCY_ALLOWANCE_HDA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VIC_0 */
0x000000ff, /* MC_LATENCY_ALLOWANCE_VI2_0 */
0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2_1 */
0x000000ef, /* MC_LATENCY_ALLOWANCE_ISP2B_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_ISP2B_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_0 */
0x00ee00ef, /* MC_LATENCY_ALLOWANCE_VDE_1 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_2 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_VDE_3 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_SATA_0 */
0x00ff00ff, /* MC_LATENCY_ALLOWANCE_AFI_0 */
},
0x00000042, /* EMC_ZCAL_WAIT_CNT after clock change */
0x001fffff, /* EMC_AUTO_CAL_INTERVAL */
0x00000802, /* EMC_CTT_TERM_CTRL */
0x73240000, /* EMC_CFG */
0x000008c5, /* EMC_CFG_2 */
0x00040128, /* EMC_SEL_DPD_CTRL */
0x002c0068, /* EMC_CFG_DIG_DLL */
0x00000008, /* EMC_BGBIAS_CTL0 */
0x00000000, /* EMC_AUTO_CAL_CONFIG2 */
0x00000000, /* EMC_AUTO_CAL_CONFIG3 */
0xa1430000, /* EMC_AUTO_CAL_CONFIG */
0x80001221, /* Mode Register 0 */
0x80100003, /* Mode Register 1 */
0x80200008, /* Mode Register 2 */
0x00000000, /* Mode Register 4 */
},
{
0x18, /* V5.0.12 */
"03_102000_02_V5.0.12_V0.9", /* DVFS table version */
102000, /* SDRAM frequency */
800, /* min voltage */
800, /* gpu min voltage */
"pllp_out0", /* clock source id */
0x40000006, /* CLK_SOURCE_EMC */
164, /* number of burst_regs */
31, /* number of up_down_regs */
{
0x00000004, /* EMC_RC */
0x0000001a, /* EMC_RFC */
0x00000000, /* EMC_RFC_SLR */
0x00000003, /* EMC_RAS */
0x00000001, /* EMC_RP */
0x00000004, /* EMC_R2W */
0x0000000a, /* EMC_W2R */
0x00000003, /* EMC_R2P */
0x0000000b, /* EMC_W2P */
0x00000001, /* EMC_RD_RCD */
0x00000001, /* EMC_WR_RCD */
0x00000003, /* EMC_RRD */
0x00000003, /* EMC_REXT */
0x00000000, /* EMC_WEXT */
0x00000006, /* EMC_WDV */
0x00000006, /* EMC_WDV_MASK */