Verilog Implementation of Run Length Encoding for RGB Image Compression

ES-203 Computer Organization & Architecture CNN on FPGA board

Router 1 x 3 verilog implementation

FPGA Guide

RISCV CPU implementation tutorial steps for Cologne Chip Gatemate E1, adopted from https://github.com/BrunoLevy/learn-fpga

基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。

My experiments with Nexys4 DDR Artix-7 FPGA Board

UART - RTL Design and Verification

⚡️Code release for Accelerating CNNs on FPGA [Published in Research in Intelligent and Computing in Engineering 2020]

Collection of my projects that was made as a part of Warsaw University FPGA course

probable journey of RTL coding ft. Chandra Prakash

This project proposes to demonstrate the capabilities and scope of Verilog HDL by implementing the control system of an automatic washing machine. The above mentioned objective by implementing the Control System of an automatic washing using the Finite State Machine model. The washing machine control system generates all the control signals requ…

A simplified RISC-V processor implemented in Verilog and deployed on the DE-2 SoC FPGA board.

Vertex 6 FPGA GTx Transciever Simulation in Xilinx ISE using Xilinx IP Core

A collection of practical sessions exploring FPGA programming and MIPS-based systems using the ALTERA Cyclone V DE-1 SoC board.

Exploring both MATLAB and Vivado Verilog in designing a Direct Digital Synthesizer (DDS) system with a FIR low-pass filter. This project goes into digital system design, signal processing, and hardware implementation.

This project implements a simple RISC-V processor for FPGAs. It supports the RV32I base instruction set and is designed for educational and experimental purposes.

Custom graphics driver using Verilog on Xilinx FPGA platform.

🎛️ FPGAs are an interesting invention that is expected to revolutionize the digital industry. This series will focus on building the 8-bit computer that Ben Eater built on his youtube channel. However, it will be done not with actual chips and hardware, but with Verilog code and FPGA simulations.

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.