Skip to content
New issue

Have a question about this project? # for a free GitHub account to open an issue and contact its maintainers and the community.

#

By clicking “#”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? # to your account

Jump to bottom

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1854

Merged
merged 17 commits into from
May 13, 2024
Merged

Support Chisel6 for RTL-sim/VLSI/FPGA flows #1854

merged 17 commits into from
May 13, 2024

Conversation

jerryz123
Copy link
Contributor

@jerryz123 jerryz123 commented Apr 19, 2024 •
edited
Loading

A more incremental approach than in #1769 .

Firesim still uses chisel3, for now. A upcoming PR will switch over firesim to chisel6 as well.

Merge after #1860

Related PRs / Issues:

Type of change:

  • Bug fix
  • New feature
  • Other enhancement

Impact:

  • RTL change
  • Software change (RISC-V software)
  • Build system change
  • Other

Contributor Checklist:

  • Did you set main as the base branch?
  • Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
  • Did you state the type-of-change/impact?
  • Did you delete any extraneous prints/debugging code?
  • Did you mark the PR with a changelog: label?
  • (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
  • (If applicable) Did you add documentation for the feature?
  • (If applicable) Did you add a test demonstrating the PR?
  • (If applicable) Did you mark the PR as Please Backport?

@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 3 times, most recently from 4ccf6ff to 7ea35a7 Compare April 19, 2024 18:40
@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 4 times, most recently from f110f29 to 9f022c3 Compare April 22, 2024 17:13
@jerryz123
Copy link
Contributor Author

@lordspacehog

@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 7 times, most recently from d454017 to 21c14ac Compare April 23, 2024 21:55
@jerryz123 jerryz123 changed the title [WIP] Second attempt at chisel6 Support Chisel6 for RTL-sim/VLSI/FPGA flows Apr 23, 2024
@jerryz123 jerryz123 marked this pull request as ready for review April 23, 2024 22:40
@jerryz123 jerryz123 mentioned this pull request Apr 24, 2024
Closed
16 tasks
abejgonzalez
abejgonzalez reviewed Apr 30, 2024
View reviewed changes
.github/workflows/chipyard-full-flow.yml
@@ -61,8 +61,8 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'

setup-repo:
name: setup-repo
full-flow:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why do this? I think having it in separate steps makes it easier to read in the UI and makes it clearer what to do when adding to this CI a new task/job

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I kept experiencing failures in the build caching between the two jobs. I can poke around more

Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Update on this?

.github/workflows/chipyard-run-tests.yml
@@ -800,29 +777,6 @@ jobs:
group-key: "group-peripherals"
project-key: "chipyard-llcchiplet"

chipyard-sha3-run-tests:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Why are SHA3 and Mempress getting removed?

Copy link
Contributor Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

They use too many deprecated chisel2 APIs.

@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 2 times, most recently from 0cc3911 to 1551830 Compare April 30, 2024 02:50
@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 2 times, most recently from ad59f6b to 6616dcd Compare May 12, 2024 19:50
abejgonzalez
abejgonzalez approved these changes May 13, 2024
View reviewed changes
Copy link
Contributor

@abejgonzalez abejgonzalez left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Couple of clarification Qs. Otherwise, SFTM.

.github/workflows/chipyard-full-flow.yml
@@ -61,8 +61,8 @@ jobs:
- '**/.gitignore'
- '.github/ISSUE_TEMPLATE/**'

setup-repo:
name: setup-repo
full-flow:
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Update on this?

build.sbt
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation, mempress, barf, shuttle, caliptra_aes)
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

What's the plan to re-integrate Mempress/SHA3?

@jerryz123
Copy link
Contributor Author

@abejgonzalez The CI failure is weird. Its like the chisel source gets corrupted between the setup-repo and dependent steps. See here: https://github.com/ucb-bar/chipyard/actions/runs/9053829746/job/24873173139

There is no plan on updating sha3. Someone interested in updating that repo is free to do so, and can open a PR reintegrating it.
I've updated mempress here: ucb-bar/mempress#4, it was not as challenging as it initially looked.

@jerryz123 jerryz123 force-pushed the chisel6-attempt2 branch 2 times, most recently from 2e6ddcf to bd37aa5 Compare May 13, 2024 18:37
jerryz123 added 15 commits May 13, 2024 12:47
@jerryz123 jerryz123 merged commit e2f4ea6 into main May 13, 2024
50 of 53 checks passed
@jerryz123 jerryz123 deleted the chisel6-attempt2 branch May 13, 2024 22:10
# for free to join this conversation on GitHub. Already have an account? # to comment
Reviewers

@abejgonzalez abejgonzalez abejgonzalez approved these changes

@joonho3020 joonho3020 Awaiting requested review from joonho3020

Assignees
No one assigned
Labels
changelog:added
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.
2 participants
@jerryz123 @abejgonzalez