doesn't deal with for loops with multiple initializations

[pbreuer]

sv2v doesn't seem to like this example from https://www.chipverify.com/systemverilog/systemverilog-for-loop or similar:

               for (int i = 0, j = 2; i < $size(array); i++) begin
			array[i][j] = "0";
                        $display ("array[%0d] = %s, %0dth index replaced by 0", i, array[i], j);
		end

I'm not trying exactly that, but that's the spirit and it is what I was following for format.
It seems to be objecting to the comma, not the type declaration, and it happens both without the type declaration and with it. I don't think sv2v handles inline declarations there anyway?

Multiple increments are also legal. Is this a "which standard" question? That page claims "There can be multiple initializations done in the first part of a for loop" (as in C).

The error from sv2v is just a parse pointer: "Parse error: unexpected token ',' (Sym_comma)"

Regards

PTB

[zachjs]

Thank you for filing this issue! I definitely intend to support this syntax:

sv2v/src/Convert/ForAsgn.hs

Lines 4 to 6 in aa0a885

	- Verilog-2005 requires that for loops have have one initialization and one
	- incrementation. If there are excess initializations, they are turned into
	- preceding statements. If there is no loop variable, a dummy loop variable is

so I suspect I'm missing something. In fact, both "multiple initializations" and "multiple increments" are supported.

For example, when I convert:

module top;
    initial
        for (int i = 0, j = 2; i < 5; j++, i++)
            $display("i=%0d j=%0d", i, j);
endmodule

through sv2v, I get:

module top;
	function automatic signed [31:0] sv2v_cast_32_signed;
		input reg signed [31:0] inp;
		sv2v_cast_32_signed = inp;
	endfunction
	initial begin : sv2v_autoblock_1
		reg signed [31:0] i;
		reg signed [31:0] j;
		i = 0;
		for (j = 2; i < 5; {j, i} = {sv2v_cast_32_signed(j + 1), sv2v_cast_32_signed(i + 1)})
			$display("i=%0d j=%0d", i, j);
	end
endmodule

When I run that output through iverilog, I get:

i=0 j=2
i=1 j=3
i=2 j=4
i=3 j=5
i=4 j=6

For reference, I'm using sv2v v0.0.12-27-g4ec99fc and iverilog 13.0 (devel) (s20221226-513-gef7f0a8f3).

Is it possible that the parse error is caused by a different part of the input? (Perhaps the source location sv2v gives is bad?) What sv2v --version are you using?