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To recreate the issue clone the following repo and follow the provided build steps. The error arises because the particular cast type used in the design is not supported by Yosys's Verilog frontend, leading Yosys to throw an error. Note that the sv2v tool is used as a pre-build hook in FuseSoC to preprocess the source files before they are passed to Yosys. For the exact command line invocation, please refer to the script at sw/sv2vpre.py.
The issue is reocurring and not limited to the example provided below. I'm not sure if this is only a missing feature or a bug.
Example input:
assign axi_lite_resp_o = '{
aw_ready: axi_req_valid[WR] & axi_req_ready[WR], // if AXI AW & W valid & tree gnt_o[WR]
w_ready: axi_req_valid[WR] & axi_req_ready[WR], // if AXI AW & W valid & tree gnt_o[WR]
b: '{resp: axi_bresp}, // from spill reg
b_valid: axi_bresp_valid, // from spill reg
ar_ready: axi_req_valid[RD] & axi_req_ready[RD], // if AXI AR valid and tree gnt[RD]
r: '{data: axi_rresp.data, resp: axi_rresp.resp}, // from spill reg
r_valid: axi_rresp_valid // from spill reg
};
Thank you for filing this issue! sv2v absolutely supports struct conversions, including the struct patterns demonstrated here. I would greatly appreciate it if you could narrow down the scale of this reproducer. Ideally, this reproducer would not require outside scripts or software, and would span at most a few files. Do you think that is doable here?
To recreate the issue clone the following repo and follow the provided build steps. The error arises because the particular cast type used in the design is not supported by Yosys's Verilog frontend, leading Yosys to throw an error. Note that the sv2v tool is used as a pre-build hook in FuseSoC to preprocess the source files before they are passed to Yosys. For the exact command line invocation, please refer to the script at sw/sv2vpre.py.
The issue is reocurring and not limited to the example provided below. I'm not sure if this is only a missing feature or a bug.
Example input:
Example output:
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