From 02ddc718c28a96b3c8c26055143abe30768485e5 Mon Sep 17 00:00:00 2001 From: Peter Gadfort Date: Fri, 16 Feb 2024 00:11:52 -0500 Subject: [PATCH] remove switchboard submodule and use switchboard-hw only --- .gitmodules | 3 --- lumi/testbench/test_lumi.py | 2 -- lumi/testbench/test_lumi_rnd.py | 2 -- submodules/switchboard | 1 - umi/testbench/test_crossbar.py | 4 +--- umi/testbench/test_fifo.py | 4 +--- umi/testbench/test_fifo_flex.py | 4 +--- umi/testbench/test_mem_agent.py | 4 +--- umi/testbench/test_regif.py | 4 +--- utils/testbench/test_umi2tl_np.py | 2 +- utils/testbench/test_umi_address_remap.py | 3 +-- utils/testbench/test_umi_packet_merge_greedy.py | 2 +- 12 files changed, 8 insertions(+), 27 deletions(-) delete mode 160000 submodules/switchboard diff --git a/.gitmodules b/.gitmodules index 89316f0..c29687a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,6 +1,3 @@ [submodule "submodules/lambdalib"] path = submodules/lambdalib url = git@github.com:siliconcompiler/lambdalib.git -[submodule "submodules/switchboard"] - path = submodules/switchboard - url = git@github.com:zeroasiccorp/switchboard.git diff --git a/lumi/testbench/test_lumi.py b/lumi/testbench/test_lumi.py index 77919db..15c83b1 100755 --- a/lumi/testbench/test_lumi.py +++ b/lumi/testbench/test_lumi.py @@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False): else: raise ValueError('Invalid topology') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/lumi/testbench/test_lumi_rnd.py b/lumi/testbench/test_lumi_rnd.py index 79d55b1..7a80b55 100755 --- a/lumi/testbench/test_lumi_rnd.py +++ b/lumi/testbench/test_lumi_rnd.py @@ -27,11 +27,9 @@ def build_testbench(topo="2d", trace=False): else: raise ValueError('Invalid topology') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') dut.add('option', option, EX_DIR / '..' / 'umi' / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/submodules/switchboard b/submodules/switchboard deleted file mode 160000 index dd5a7b1..0000000 --- a/submodules/switchboard +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dd5a7b193c091a7c3c572151e9930a3486097f9d diff --git a/umi/testbench/test_crossbar.py b/umi/testbench/test_crossbar.py index 2c41224..4c5c2db 100755 --- a/umi/testbench/test_crossbar.py +++ b/umi/testbench/test_crossbar.py @@ -14,7 +14,7 @@ THIS_DIR = Path(__file__).resolve().parent def build_testbench(): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('..') EX_DIR = EX_DIR.resolve() @@ -22,10 +22,8 @@ def build_testbench(): # Set up inputs dut.input('testbench_crossbar.sv') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/umi/testbench/test_fifo.py b/umi/testbench/test_fifo.py index 46ae18f..23f49bf 100755 --- a/umi/testbench/test_fifo.py +++ b/umi/testbench/test_fifo.py @@ -13,7 +13,7 @@ def build_testbench(): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('..') EX_DIR = EX_DIR.resolve() @@ -21,10 +21,8 @@ def build_testbench(): # Set up inputs dut.input('testbench_fifo.sv') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/umi/testbench/test_fifo_flex.py b/umi/testbench/test_fifo_flex.py index a15b21f..f1c1223 100755 --- a/umi/testbench/test_fifo_flex.py +++ b/umi/testbench/test_fifo_flex.py @@ -13,7 +13,7 @@ def build_testbench(): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('..') EX_DIR = EX_DIR.resolve() @@ -21,10 +21,8 @@ def build_testbench(): # Set up inputs dut.input('testbench_fifo_flex.sv') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/umi/testbench/test_mem_agent.py b/umi/testbench/test_mem_agent.py index bc61572..c28fef6 100755 --- a/umi/testbench/test_mem_agent.py +++ b/umi/testbench/test_mem_agent.py @@ -13,7 +13,7 @@ def build_testbench(): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('..') EX_DIR = EX_DIR.resolve() @@ -21,10 +21,8 @@ def build_testbench(): # Set up inputs dut.input('testbench_mem_agent.sv') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/umi/testbench/test_regif.py b/umi/testbench/test_regif.py index 9c209cb..c721892 100755 --- a/umi/testbench/test_regif.py +++ b/umi/testbench/test_regif.py @@ -13,7 +13,7 @@ def build_testbench(): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('..') EX_DIR = EX_DIR.resolve() @@ -21,10 +21,8 @@ def build_testbench(): # Set up inputs dut.input('testbench_regif.sv') - dut.input(EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'rtl') - dut.add('option', option, EX_DIR / '..' / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilog') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'ramlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'stdlib' / 'rtl') dut.add('option', option, EX_DIR / '..' / 'submodules' / 'lambdalib' / 'lambdalib' / 'vectorlib' / 'rtl') diff --git a/utils/testbench/test_umi2tl_np.py b/utils/testbench/test_umi2tl_np.py index c4936a4..29096a8 100755 --- a/utils/testbench/test_umi2tl_np.py +++ b/utils/testbench/test_umi2tl_np.py @@ -11,7 +11,7 @@ def build_testbench(topo="2d"): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=False) EX_DIR = Path('../..') EX_DIR = EX_DIR.resolve() diff --git a/utils/testbench/test_umi_address_remap.py b/utils/testbench/test_umi_address_remap.py index d98a016..061624d 100755 --- a/utils/testbench/test_umi_address_remap.py +++ b/utils/testbench/test_umi_address_remap.py @@ -11,7 +11,7 @@ def build_testbench(topo="2d"): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=True) EX_DIR = Path('../..') @@ -26,7 +26,6 @@ def build_testbench(topo="2d"): else: raise ValueError('Invalid topology') - dut.input(EX_DIR / 'submodules' / 'switchboard' / 'examples' / 'common' / 'verilator' / 'testbench.cc') for option in ['ydir', 'idir']: dut.add('option', option, EX_DIR / 'umi' / 'rtl') dut.add('option', option, EX_DIR / 'utils' / 'rtl') diff --git a/utils/testbench/test_umi_packet_merge_greedy.py b/utils/testbench/test_umi_packet_merge_greedy.py index 0474f7a..0f70ef3 100755 --- a/utils/testbench/test_umi_packet_merge_greedy.py +++ b/utils/testbench/test_umi_packet_merge_greedy.py @@ -11,7 +11,7 @@ def build_testbench(topo="2d"): - dut = SbDut('testbench') + dut = SbDut('testbench', default_main=False) EX_DIR = Path('../..')