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Emit LLVM bitcode without using LLVM #19031

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Feb 24, 2024
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8feae5d
LLVM: Assign correct values to enum/union tags
antlilja Aug 17, 2023
1d94e9e
LLVM: Make sure child types get added first
antlilja Aug 14, 2023
9ccd715
LLVM Builder: Make Type.Simple reflect LLVM codes
antlilja Aug 26, 2023
2801bf6
LLVM Builder: Add strtab helper to String
antlilja Aug 26, 2023
fd3b81f
LLVM Builder: Add toLlvm helper to Alignment
antlilja Aug 26, 2023
6df8302
Fixed values in AtomicOrdering enum
antlilja Jan 19, 2024
ff76ba6
Added values to AtomicRmw.Operation enum fields
antlilja Jan 19, 2024
52e8434
Added opcode functions to Instruction/Constant.Tag
antlilja Jan 19, 2024
c57b4e7
Builder: Add function_attributes_set
antlilja Jan 19, 2024
423c2c3
Made .block = false in WipFunction.hasResultWip
antlilja Jan 19, 2024
7cb8813
Added value_indices and valueIndex to Function
antlilja Jan 19, 2024
ec5a433
Fix FastMath packed struct
antlilja Jan 23, 2024
1502959
LLVM Builder: Add integer values to more enums fields
antlilja Feb 19, 2024
4653fc4
LLVM Builder: Add dbg.declare and dbg.value intrinsics
antlilja Feb 19, 2024
2396806
Add LLVM bitcode writer
antlilja Aug 13, 2023
5bd2a7c
LLVM IR specific bitcode
antlilja Aug 13, 2023
b4369df
LLVM: Add toBitcode to Builder
antlilja Aug 13, 2023
a456631
LLVM Builder: Add debug/metadata system
antlilja Feb 19, 2024
049cad4
LLVM Builder: Add debug locations to instructions
antlilja Feb 19, 2024
d305548
LLVM: Emit bitcode even if libllvm is not present
antlilja Aug 13, 2023
c16818d
Add LLVM bindings for parsing LLVM bitcode
antlilja Feb 19, 2024
c11c7a2
codegen/llvm: Remove use of DIBuilder and output bin by parsing bitcode
antlilja Feb 19, 2024
d35080b
LLVM: Add Metadata/Debug bitcode IR
antlilja Feb 21, 2024
626c3f7
LLVM Builder: Emit debug info and metadata
antlilja Feb 21, 2024
f6d275b
LLVM: Remove use of LLVM in Builder
antlilja Feb 21, 2024
713a555
LLVM: Remove unused from llvm/bindings.zig and zig_llvm.h/.cpp
antlilja Feb 21, 2024
48bd0ed
llvm: fix builds that don't link with libllvm
jacobly0 Feb 21, 2024
e57f553
LLVM Builder: Rework MetadataString to not rely on String
antlilja Feb 21, 2024
5e9d0da
LLVM Builder: Correctly emit debug subranges
antlilja Feb 21, 2024
53f6071
LLVM Builder: Emit debug vector types with DIVector flag
antlilja Feb 21, 2024
a907353
LLVM Builder: Fix on 32-bit systems
antlilja Feb 21, 2024
4b215e3
Builder: support printing metadata in llvm ir
jacobly0 Feb 22, 2024
92eec8d
LLVM Builder: Emit type for debug subprogram
antlilja Feb 22, 2024
de536e8
LLVM Builder: Emit metadata kinds and function metadata attachments
antlilja Feb 22, 2024
6cc51d3
LLVM: Set new debug location after inlining
antlilja Feb 22, 2024
69a6f31
Builder: fix llvm ir value names
jacobly0 Feb 22, 2024
2ab982e
Revert build.zig to old 7GB value
antlilja Feb 22, 2024
83e66d3
Builder: fix bitcode strtab
jacobly0 Feb 22, 2024
dbfa323
Builder: fix float constants in llvm ir
jacobly0 Feb 22, 2024
c894df5
Builder: fix debug location of the first instruction in a block
jacobly0 Feb 23, 2024
0ba2185
LLVM Builder: Formatting
antlilja Feb 23, 2024
dfde194
LLVM Builder: Make some Metadata no longer be distinct
antlilja Feb 23, 2024
8d0f660
Builder: sync distinct bits with previous implementation
jacobly0 Feb 23, 2024
be4ad23
Builder: fix inconsequential llvm ir metadata syntax
jacobly0 Feb 23, 2024
1d4a7e1
llvm: revert bad cleanup
jacobly0 Feb 23, 2024
43daed6
Builder: change tuple metadata to not be inlined in llvm ir
jacobly0 Feb 23, 2024
6abb432
Builder: implement opaque structs in bitcode
jacobly0 Feb 23, 2024
800495a
Builder: fix minor llvm ir syntax errors
jacobly0 Feb 23, 2024
7f3ade6
Builder: fix x86_fp80 constants in bitcode
jacobly0 Feb 23, 2024
03eb332
Builder: fix aliases in bitcode
jacobly0 Feb 23, 2024
f644263
Builder: fix llvm ir/bc difference with allocas
jacobly0 Feb 23, 2024
2c67a1e
llvm: optimize i32 constants
jacobly0 Feb 23, 2024
a8708db
Builder: fix inconsequential llvm ir flag syntax
jacobly0 Feb 23, 2024
ceb2c03
llvm: revert debug file path resolution changes
jacobly0 Feb 23, 2024
9b39e82
Builder: Emit metadata attachment for globals
antlilja Feb 24, 2024
7e9f321
Builder: fix bitcode widths
jacobly0 Feb 24, 2024
edb6486
BitcodeWriter: cleanup type widths
jacobly0 Feb 24, 2024
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9 changes: 4 additions & 5 deletions lib/std/meta.zig
Original file line number Diff line number Diff line change
Expand Up @@ -460,13 +460,12 @@ test "std.meta.FieldType" {
try testing.expect(FieldType(U, .d) == *const u8);
}

pub fn fieldNames(comptime T: type) *const [fields(T).len][]const u8 {
pub fn fieldNames(comptime T: type) *const [fields(T).len][:0]const u8 {
return comptime blk: {
const fieldInfos = fields(T);
var names: [fieldInfos.len][]const u8 = undefined;
for (fieldInfos, 0..) |field, i| {
names[i] = field.name;
}
var names: [fieldInfos.len][:0]const u8 = undefined;
// This concat can be removed with the next zig1 update.
for (&names, fieldInfos) |*name, field| name.* = field.name ++ "";
break :blk &names;
};
}
Expand Down
54 changes: 31 additions & 23 deletions src/arch/x86_64/CodeGen.zig
Original file line number Diff line number Diff line change
Expand Up @@ -16683,36 +16683,44 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
else => null,
};
defer if (elem_lock) |lock| self.register_manager.unlockReg(lock);
const elem_reg = registerAlias(
try self.copyToTmpRegister(elem_ty, mat_elem_mcv),
elem_abi_size,
);

const elem_extra_bits = self.regExtraBits(elem_ty);
if (elem_bit_off < elem_extra_bits) {
try self.truncateRegister(elem_ty, elem_reg);
{
const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
const temp_alias = registerAlias(temp_reg, elem_abi_size);
const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg);
defer self.register_manager.unlockReg(temp_lock);

if (elem_bit_off < elem_extra_bits) {
try self.truncateRegister(elem_ty, temp_alias);
}
if (elem_bit_off > 0) try self.genShiftBinOpMir(
.{ ._l, .sh },
elem_ty,
.{ .register = temp_alias },
Type.u8,
.{ .immediate = elem_bit_off },
);
try self.genBinOpMir(
.{ ._, .@"or" },
elem_ty,
.{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } },
.{ .register = temp_alias },
);
}
if (elem_bit_off > 0) try self.genShiftBinOpMir(
.{ ._l, .sh },
elem_ty,
.{ .register = elem_reg },
Type.u8,
.{ .immediate = elem_bit_off },
);
try self.genBinOpMir(
.{ ._, .@"or" },
elem_ty,
.{ .load_frame = .{ .index = frame_index, .off = elem_byte_off } },
.{ .register = elem_reg },
);
if (elem_bit_off > elem_extra_bits) {
const reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
const temp_reg = try self.copyToTmpRegister(elem_ty, mat_elem_mcv);
const temp_alias = registerAlias(temp_reg, elem_abi_size);
const temp_lock = self.register_manager.lockRegAssumeUnused(temp_reg);
defer self.register_manager.unlockReg(temp_lock);

if (elem_extra_bits > 0) {
try self.truncateRegister(elem_ty, registerAlias(reg, elem_abi_size));
try self.truncateRegister(elem_ty, temp_alias);
}
try self.genShiftBinOpMir(
.{ ._r, .sh },
elem_ty,
.{ .register = reg },
.{ .register = temp_reg },
Type.u8,
.{ .immediate = elem_abi_bits - elem_bit_off },
);
Expand All @@ -16723,7 +16731,7 @@ fn airAggregateInit(self: *Self, inst: Air.Inst.Index) !void {
.index = frame_index,
.off = elem_byte_off + @as(i32, @intCast(elem_abi_size)),
} },
.{ .register = reg },
.{ .register = temp_alias },
);
}
}
Expand Down
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