csr/bus: Take data width into account for register writes #30
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When using csr.Multiplexer with a data width greater than 8, writes should be performed when chunk_addr is matched to the start of a chunk.
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When using csr.Multiplexer with a data width greater than 8, writes should be performed when chunk_addr is matched to the start of a chunk.
I came across this when using a 32 bit wide data bus for both CSR and wishbone. I added a test case to match what I was doing.