brutzelkarte.ldf

<?xml version="1.0" encoding="UTF-8"?>
<BaliProject version="3.2" title="brutzelkarte" device="LCMXO2-7000HC-6TG144C" default_implementation="impl1">
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    <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
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        <Source name="N64_CIC.vhd" type="VHDL" type_short="VHDL">
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        <Source name="N64_FlashRam.vhd" type="VHDL" type_short="VHDL">
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        <Source name="rom_buffer.vhd" type="VHDL" type_short="VHDL">
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        <Source name="sram_controller_wb.vhd" type="VHDL" type_short="VHDL">
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        <Source name="top.vhd" type="VHDL" type_short="VHDL">
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        <Source name="s25fl256s_x2.vhd" type="VHDL" type_short="VHDL">
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        <Source name="ipexpress/cmd_fifo/cmd_fifo.ipx" type="IPX_Module" type_short="IPX">
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        <Source name="stx_etx_rcv.vhd" type="VHDL" type_short="VHDL">
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        <Source name="stx_etx_send.vhd" type="VHDL" type_short="VHDL">
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        <Source name="uart_access.vhd" type="VHDL" type_short="VHDL">
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        <Source name="flash_write_buffer.vhd" type="VHDL" type_short="VHDL">
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        <Source name="ipexpress/pll0/pll0.ipx" type="IPX_Module" type_short="IPX">
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        <Source name="ipexpress/efb0/efb0.ipx" type="IPX_Module" type_short="IPX">
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        <Source name="i2c_master.vhd" type="VHDL" type_short="VHDL">
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        <Source name="mcp7940n.vhd" type="VHDL" type_short="VHDL">
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        <Source name="lm8_cic/soc/lm8_cic.v" type="Verilog" type_short="Verilog">
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        <Source name="brutzelkarte.vhd" type="VHDL" type_short="VHDL">
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        </Source>
        <Source name="ipexpress/uart_fifo/uart_fifo.ipx" type="IPX_Module" type_short="IPX">
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        </Source>
        <Source name="uart_fifo_level_tracking.vhd" type="VHDL" type_short="VHDL">
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        </Source>
        <Source name="brutzelkarte.lpf" type="Logic Preference" type_short="LPF">
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        </Source>
    </Implementation>
    <Strategy name="Strategy1" file="brutzelkarte1.sty"/>
</BaliProject>