8357056: RISC-V: Asm fixes - load/store width

[robehn]

Hi, please consider.

While working on #25252, I notice:

• Major op code was just repeat
• Width coded in binary
• Stores have mixed up rs1 and rs2
• Bonus, fsd used a macro for no reason

I think this improves readability.

Tested tier1

Thanks, Robbin

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Progress

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Issue

• JDK-8357056: RISC-V: Asm fixes - load/store width (Enhancement - P5)

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$ git fetch https://git.openjdk.org/jdk.git pull/25253/head:pull/25253
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Update a local copy of the PR:
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$ git pull https://git.openjdk.org/jdk.git pull/25253/head

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Checkout this PR locally:
$ git pr checkout 25253

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https://git.openjdk.org/jdk/pull/25253.diff

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