chipdesign

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RISC-V Linux SoC, marchID: 0x2b

linux asic cpu fpga x11 riscv verilog xv6 systemverilog mmu soc bare-metal rv32ima chipdesign tinytapeout sv32

Skywaters 130nm Klayout PDK

pdk skywaters chipdesign

Designinig a Pipeline in-order 5 stage RISC-V core RV32I-MAF

core assembly riscv rtl isa systemverilog vlsi risc-v pipline vlsi-design chipdesign

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

opensource sql sqlite dpi eda sqlite3 systemverilog uvm ipxact uvm-ral-model hardwareverification chipdesign asicdesig designverification

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