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yury committed Nov 25, 2024
1 parent 54c5674 commit ac2f1b8
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions cidre/src/core_audio/hardware.rs
Original file line number Diff line number Diff line change
Expand Up @@ -75,7 +75,7 @@ impl Obj {
}
}

pub fn prop_bool(&self, address: &PropAddr) -> os::Result<bool> {
pub fn bool_prop(&self, address: &PropAddr) -> os::Result<bool> {
let res: u32 = self.prop(address)?;
Ok(res == 1)
}
Expand Down Expand Up @@ -249,15 +249,15 @@ impl Process {
}

pub fn is_running(&self) -> os::Result<bool> {
self.prop_bool(&PropSelector::PROCESS_IS_RUNNING.global_addr())
self.bool_prop(&PropSelector::PROCESS_IS_RUNNING.global_addr())
}

pub fn is_running_input(&self) -> os::Result<bool> {
self.prop_bool(&PropSelector::PROCESS_IS_RUNNING_INPUT.global_addr())
self.bool_prop(&PropSelector::PROCESS_IS_RUNNING_INPUT.global_addr())
}

pub fn is_running_output(&self) -> os::Result<bool> {
self.prop_bool(&PropSelector::PROCESS_IS_RUNNING_OUTPUT.global_addr())
self.bool_prop(&PropSelector::PROCESS_IS_RUNNING_OUTPUT.global_addr())
}

pub fn devices(&self) -> os::Result<Vec<Device>> {
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