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Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
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@Abdulwadoodd
Abdulwadoodd committed May 24, 2024
1 parent 38e7345 commit 1dc8682
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Showing 19 changed files with 112 additions and 178 deletions.
26 changes: 13 additions & 13 deletions .github/workflows/arch-tests.yml
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Expand Up @@ -27,23 +27,23 @@ jobs:
- name: Build spike
run: |
ci-tests/build-spike
test/act_cross_check/build-spike
echo $GITHUB_WORKSPACE/install/bin >> $GITHUB_PATH
- name: Build Sail
run: |
ci-tests/build-sail
test/act_cross_check/build-sail
echo $GITHUB_WORKSPACE/c_emulator >> $GITHUB_PATH
- name: Init arch-tests
run: |
cd ci-tests/riscof
cd test/act_cross_check/riscof
git clone https://github.com/riscv-non-isa/riscv-arch-test
cd riscv-arch-test && git fetch --tags && git checkout tags/3.8.10
cd riscv-arch-test && git fetch --tags && git checkout tags/3.9
- name: Run RV32E
run: |
cd ci-tests/riscof
cd test/act_cross_check/riscof
sed -i 's/\(ispec=\)\(.*\)/\1spike\/spike_isa32e.yaml/' config.ini
./run-tests.sh rv32e_work
Expand All @@ -52,12 +52,12 @@ jobs:
with:
name: artifacts_rv32e
path: |
ci-tests/riscof/rv32e_work/report.html
ci-tests/riscof/rv32e_work/style.css
test/act_cross_check/riscof/rv32e_work/report.html
test/act_cross_check/riscof/rv32e_work/style.css
- name: Run RV32I
run: |
cd ci-tests/riscof
cd test/act_cross_check/riscof
sed -i 's/\(ispec=\)\(.*\)/\1spike\/spike_isa32.yaml/' config.ini
./run-tests.sh rv32i_work
Expand All @@ -66,12 +66,12 @@ jobs:
with:
name: artifacts_rv32i
path: |
ci-tests/riscof/rv32i_work/report.html
ci-tests/riscof/rv32i_work/style.css
test/act_cross_check/riscof/rv32i_work/report.html
test/act_cross_check/riscof/rv32i_work/style.css
- name: Run RV64I
run: |
cd ci-tests/riscof
cd test/act_cross_check/riscof
sed -i 's/\(ispec=\)\(.*\)/\1spike\/spike_isa64.yaml/' config.ini
./run-tests.sh rv64i_work
Expand All @@ -80,5 +80,5 @@ jobs:
with:
name: artifacts_rv64i
path: |
ci-tests/riscof/rv64i_work/report.html
ci-tests/riscof/rv64i_work/style.css
test/act_cross_check/riscof/rv64i_work/report.html
test/act_cross_check/riscof/rv64i_work/style.css
1 change: 1 addition & 0 deletions .gitignore
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Expand Up @@ -7,3 +7,4 @@ _sbuild/
*.o
*.a
/z3_problems
__pycache__/
8 changes: 4 additions & 4 deletions build_simulators.sh
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Expand Up @@ -10,8 +10,8 @@ function test_build () {
fi
}

test_build make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32
test_build make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" ARCH=RV64 ocaml_emulator/riscv_ocaml_sim_RV64
test_build make -j"$(nproc 2> /dev/null)" ARCH=RV32 ocaml_emulator/riscv_ocaml_sim_RV32
test_build make -j"$(nproc 2> /dev/null)" ARCH=RV64 ocaml_emulator/riscv_ocaml_sim_RV64

test_build make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" ARCH=RV32 c_emulator/riscv_sim_RV32
test_build make -j"$(nproc 2> /dev/null || sysctl -n hw.ncpu)" ARCH=RV64 c_emulator/riscv_sim_RV64
test_build make -j"$(nproc 2> /dev/null)" ARCH=RV32 c_emulator/riscv_sim_RV32
test_build make -j"$(nproc 2> /dev/null)" ARCH=RV64 c_emulator/riscv_sim_RV64
14 changes: 0 additions & 14 deletions ci-tests/riscof/config.ini
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33 changes: 0 additions & 33 deletions ci-tests/riscof/sail_cSim/env/model_test.h
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0 ci-tests/build-sail → test/act_cross_check/build-sail
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0 ci-tests/build-spike → test/act_cross_check/build-spike
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14 changes: 14 additions & 0 deletions test/act_cross_check/riscof/config.ini
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@@ -0,0 +1,14 @@
[RISCOF]
ReferencePlugin=sail_csim
ReferencePluginPath=sail_csim
DUTPlugin=spike
DUTPluginPath=spike

[spike]
pluginpath=spike
ispec=spike/spike_isa32e.yaml
pspec=spike/spike_platform.yaml
target_run=1

[sail_csim]
pluginpath=sail_csim
2 changes: 1 addition & 1 deletion ci-tests/riscof/run-tests.sh → test/act_cross_check/riscof/run-tests.sh
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@@ -1,4 +1,4 @@
# !bin/bash
#!/bin/bash

set -e

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0 ci-tests/riscof/sail_cSim/env/link.ld → ..._cross_check/riscof/sail_csim/env/link.ld
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55 changes: 55 additions & 0 deletions test/act_cross_check/riscof/sail_csim/env/model_test.h
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@@ -0,0 +1,55 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

// clang-format off
#define RVMODEL_DATA_SECTION .pushsection \
.tohost, "aw", @progbits; \
.align 8; \
.global tohost; \
tohost: \
.dword 0; \
.align 8; \
.global fromhost; \
fromhost: \
.dword 0; \
.popsection; \
.align 8; \
.global begin_regstate; \
begin_regstate: \
.word 128; \
.align 8; \
.global end_regstate; \
end_regstate: \
.word 4;

// clang-format on
#define RVMODEL_HALT \
li x1, 1; \
write_tohost: \
sw x1, tohost, x3; \
j write_tohost;

#define RVMODEL_BOOT

#define RVMODEL_DATA_BEGIN \
RVMODEL_DATA_SECTION.align 4; \
.global begin_signature; \
begin_signature:

#define RVMODEL_DATA_END \
.align 4; \
.global end_signature; \
end_signature:

#define RVMODEL_IO_INIT
#define RVMODEL_IO_WRITE_STR(_R, _STR)
#define RVMODEL_IO_CHECK()
#define RVMODEL_IO_ASSERT_GPR_EQ(_S, _R, _I)
#define RVMODEL_IO_ASSERT_SFPR_EQ(_F, _R, _I)
#define RVMODEL_IO_ASSERT_DFPR_EQ(_D, _R, _I)
#define RVMODEL_SET_MSW_INT
#define RVMODEL_CLEAR_MSW_INT
#define RVMODEL_CLEAR_MTIMER_INT
#define RVMODEL_CLEAR_MEXT_INT

#endif
73 changes: 2 additions & 71 deletions ...ests/riscof/sail_cSim/riscof_sail_cSim.py → ...heck/riscof/sail_csim/riscof_sail_csim.py
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@@ -1,21 +1,11 @@
import os
import re
import shutil
import subprocess
import shlex
import logging
import random
import string
from string import Template

import riscof.utils as utils
from riscof.pluginTemplate import pluginTemplate
import riscof.constants as constants
from riscv_isac.isac import isac

logger = logging.getLogger()

class sail_cSim(pluginTemplate):
class sail_csim(pluginTemplate):
__model__ = "sail_c_simulator"
__version__ = "0.5.0"

Expand All @@ -24,7 +14,7 @@ def __init__(self, *args, **kwargs):

config = kwargs.get('config')
if config is None:
logger.error("Config node for sail_cSim missing.")
print("Please enter input file paths in configuration.")
raise SystemExit(1)
self.num_jobs = str(config['jobs'] if 'jobs' in config else 1)
self.pluginpath = os.path.abspath(config['pluginpath'])
Expand All @@ -33,9 +23,6 @@ def __init__(self, *args, **kwargs):
self.isa_spec = os.path.abspath(config['ispec']) if 'ispec' in config else ''
self.platform_spec = os.path.abspath(config['pspec']) if 'ispec' in config else ''
self.make = config['make'] if 'make' in config else 'make'
logger.debug("SAIL CSim plugin initialised using the following configuration.")
for entry in config:
logger.debug(entry+' : '+config[entry])
return sclass

def initialise(self, suite, work_dir, archtest_env):
Expand All @@ -49,74 +36,18 @@ def initialise(self, suite, work_dir, archtest_env):
-I '+self.pluginpath+'/env/\
-I ' + archtest_env

# workaround to avoid clang format error in sail-riscv CI.
# *clang suggest style that is syntactically incorrect*
# Insert the following macro at run-time.
modelTest_path = 'sail_cSim/env/model_test.h'
macro = """
#define RVMODEL_DATA_SECTION .pushsection \\
.tohost, "aw", @progbits; \\
.align 8; \\
.global tohost; \\
tohost: \\
.dword 0; \\
.align 8; \\
.global fromhost; \\
fromhost: \\
.dword 0; \\
.popsection; \\
.align 8; \\
.global begin_regstate; \\
begin_regstate: \\
.word 128; \\
.align 8; \\
.global end_regstate; \\
end_regstate: \\
.word 4;
"""
with open(modelTest_path, 'r') as file:
modelTest = file.readlines()
modelTest.insert(2, macro)
with open(modelTest_path, 'w') as file:
file.writelines(modelTest)

def build(self, isa_yaml, platform_yaml):
ispec = utils.load_yaml(isa_yaml)['hart0']
self.xlen = ('64' if 64 in ispec['supported_xlen'] else '32')
self.isa = ' ' # 'rv' + self.xlen
ilp32 = 'ilp32e ' if "E" in ispec["ISA"] else 'ilp32 '
self.compile_cmd = self.compile_cmd+' -mabi='+('lp64 ' if 64 in ispec['supported_xlen'] else ilp32)
# if "I" in ispec["ISA"]:
# self.isa += 'i'
# if "M" in ispec["ISA"]:
# self.isa += 'm'
# if "C" in ispec["ISA"]:
# self.isa += 'c'
# if "F" in ispec["ISA"]:
# self.isa += 'f'
# if "D" in ispec["ISA"]:
# self.isa += 'd'

# flag for sail-riscv to enable zcb extension.
# sail model does not yet offer flags for other extensions, supported extensions are enabled by default
if "Zcb" in ispec["ISA"]:
self.isa += ' --enable-zcb'

objdump = "riscv64-unknown-elf-objdump"
if shutil.which(objdump) is None:
logger.error(objdump+": executable not found. Please check environment setup.")
raise SystemExit(1)
compiler = "riscv64-unknown-elf-gcc"
if shutil.which(compiler) is None:
logger.error(compiler+": executable not found. Please check environment setup.")
raise SystemExit(1)
if shutil.which(self.sail_exe[self.xlen]) is None:
logger.error(self.sail_exe[self.xlen]+ ": executable not found. Please check environment setup.")
raise SystemExit(1)
if shutil.which(self.make) is None:
logger.error(self.make+": executable not found. Please check environment setup.")
raise SystemExit(1)

def runTests(self, testList, cgf_file=None):
if os.path.exists(self.work_dir+ "/Makefile." + self.name[:-1]):
os.remove(self.work_dir+ "/Makefile." + self.name[:-1])
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0 ci-tests/riscof/spike/env/link.ld → .../act_cross_check/riscof/spike/env/link.ld
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22 changes: 22 additions & 0 deletions ci-tests/riscof/spike/env/model_test.h → ...cross_check/riscof/spike/env/model_test.h
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Original file line number Diff line number Diff line change
@@ -1,6 +1,28 @@
#ifndef _COMPLIANCE_MODEL_H
#define _COMPLIANCE_MODEL_H

// clang-format off
#define RVMODEL_DATA_SECTION .pushsection \
.tohost, "aw", @progbits; \
.align 8; \
.global tohost; \
tohost: \
.dword 0; \
.align 8; \
.global fromhost; \
fromhost: \
.dword 0; \
.popsection; \
.align 8; \
.global begin_regstate; \
begin_regstate: \
.word 128; \
.align 8; \
.global end_regstate; \
end_regstate: \
.word 4;

// clang-format on
#define RVMODEL_HALT \
li x1, 1; \
write_tohost: \
Expand Down
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