add zcb tests in ci, set arch-test version

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Abdulwadoodd · May 17, 2024 · bd446c5 · bd446c5
1 parent 77d54fd
commit bd446c5
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Showing 5 changed files with 8 additions and 5 deletions.
diff --git a/.github/workflows/arch-tests.yml b/.github/workflows/arch-tests.yml
@@ -21,7 +21,7 @@ jobs:
           run: |
             sudo xargs apt-get install -y < .github/workflows/apt-packages.txt
             pip3 install git+https://github.com/riscv/riscof.git
-            wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2023.12.20/riscv64-elf-ubuntu-22.04-gcc-nightly-2023.12.20-nightly.tar.gz
+            wget -c https://github.com/riscv-collab/riscv-gnu-toolchain/releases/download/2024.04.12/riscv64-elf-ubuntu-22.04-gcc-nightly-2024.04.12-nightly.tar.gz
             tar -xzf riscv64-elf-ubuntu-22.04-gcc-nightly-2023.12.20-nightly.tar.gz
             echo $GITHUB_WORKSPACE/riscv/bin >> $GITHUB_PATH
 
@@ -38,7 +38,8 @@ jobs:
         - name: Init arch-tests
           run: |
             cd ci-tests/riscof
-            riscof arch-test --clone
+            git clone https://github.com/riscv-non-isa/riscv-arch-test
+            cd riscv-arch-test && git fetch --tags && git checkout tags/3.8.10
 
         - name: Run RV32E
           run: |

diff --git a/ci-tests/riscof/sail_cSim/riscof_sail_cSim.py b/ci-tests/riscof/sail_cSim/riscof_sail_cSim.py
@@ -134,7 +134,7 @@ def runTests(self, testList, cgf_file=None):
             sig_file = os.path.join(test_dir, self.name[:-1] + ".signature")
 
             # execute += self.sail_exe[self.xlen] + ' --test-signature={0} {1} > {2}.log 2>&1;'.format(sig_file, elf, test_name)
-            execute += self.sail_exe[self.xlen] + ' --no-trace --test-signature={0} {1} > /dev/null;'.format(sig_file, elf)
+            execute += self.sail_exe[self.xlen] + ' --enable-zcb --no-trace --test-signature={0} {1} > /dev/null;'.format(sig_file, elf)
 
             make.add_target(execute)
         make.execute_all(self.work_dir)
diff --git a/ci-tests/riscof/spike/riscof_spike.py b/ci-tests/riscof/spike/riscof_spike.py
@@ -128,6 +128,8 @@ def build(self, isa_yaml, platform_yaml):
           self.isa += '_zicond'
       if "Zicboz" in ispec["ISA"]:
           self.isa += '_zicboz'
+      if "Zfa" in ispec["ISA"]:
+          self.isa += '_zfa'
 
     def runTests(self, testList):
 

diff --git a/ci-tests/riscof/spike/spike_isa32.yaml b/ci-tests/riscof/spike/spike_isa32.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zba_Zbb_Zbc_Zbs
+  ISA: RV32IMAFDCZicsr_Zicond_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 32
   User_Spec_Version: '2.3'
   supported_xlen: [32]

diff --git a/ci-tests/riscof/spike/spike_isa64.yaml b/ci-tests/riscof/spike/spike_isa64.yaml
@@ -1,6 +1,6 @@
 hart_ids: [0]
 hart0:
-  ISA: RV64IMAFDCZicsr_Zicond_Zifencei_Zba_Zbb_Zbc_Zbs
+  ISA: RV64IMAFDCZicsr_Zicond_Zifencei_Zca_Zcb_Zba_Zbb_Zbc_Zbs
   physical_addr_sz: 56
   User_Spec_Version: '2.3'
   supported_xlen: [64]