Created by: Angelo Jacobo
Date: August 16,2021

Inside the src folder are:

• top_module.v -> Combines the camera_interface, sdram_interface, and vga_interface modules.
             key[1:0] for brightness control
             key[3:2] for contrast control
• camera_interface.v -> Configures the register of OV7670 via SCCB protocol. Pixel data is also retrieved from
            the camera and then passed to asyn_fifo module
• sdram_interface.v -> Controls the logic sequence for storing the pixel data retrieved from the camera_interface
             module and then sending it to the asyn_fifo connected to vga_interface module
• vga_interface.v -> Passes the pixel data retrieved from sdram to the vga_core module
• asyn_fifo.v -> FIFO with separate clock domains for read and write. Solves the clock domain crossing issue(see
             image below)
• i2c_top.v -> Bit-bang implementation of SCCB(which is very similar to i2c)
• sdram_controller.v -> Controller for storing to and retrieving data from SDRAM. Optimized to a memory
             bandwidth of 316MB/s
• vga_core.v -> VGA controller. Set at 640x480 @ 60fps
• top_module.ucf -> Constraint file for top_module.v

NOTE: dcm_24MHz.v , dcm_25MHz.v , and dcm_165MHz.v are PLL instantiations specific to Xilinx. Replace these files(and also the instantiation of these PLLs on the source code) when implementing this design to other FPGAs.

Logic Flow:

About:

This project implements a real-time streaming of OV7670 camera via VGA. The OV7670 is a 0.3 Megapixel camera(640x480) with 30 fps. Data pixels are stored to and retrieved from SDRAM with burst mode set to "full page"(512 words).

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