Add support for booting on T8012 (T2) SoC #425
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asdfugil
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Address some peculiarities specific to T2: - Reserved memory at top is very large, either 512 MB or 1536 MB, and only lowest 512 MB is for OS use. - Some ranges in /arm-io/ranges is not aligned to the page size. We align them ourselves instead. - On models with a screen, the framebuffer is extremely narrow at 60 pixels in width, so add a smaller logo. Signed-off-by: Nick Chan <towinchenmi@gmail.com>
- Some devices does not have a display internal or external, do not try to prepare framebuffer on it. - Describe the x86 SSD cache on T2, since any potential driver will also need that memory range to be described. For now though, it can be used as normal memory. - Only half of the memory channels are used on T2 with 1 GB of memory, and this fact must be learned at runtime because the amount of memory depends on the storage configuration of the host Mac. Signed-off-by: Nick Chan <towinchenmi@gmail.com>
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marcan
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Feb 3, 2025
| u64 cache_min = ALIGN_UP(dram_max, BIT(29)); | ||
| u64 cache_max = dram_base + dram_size; | ||
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| /* Set x86 SSD Cache as OS memory, any potential driver would need the memory described |
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This won't work with an actual driver, it just abuses this region as main memory. If a driver were to use this, it would have to be described as reserved-memory (which automatically adds it to the list if mapped).
If you intend to ever actually support ANS here, then this probably needs to be kept reserved.
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I think I will not describe this memory region for now, given that it might need new compatibles and stuff and that that part of the hardware is not well understood. In this case, this memory region only needs to be concerned while correcting mem_size_actual.
| /* Set x86 SSD Cache as OS memory, any potential driver would need the memory described | ||
| * anyways */ | ||
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| memreg[num_regions].start = cpu_to_fdt64(cache_min); |
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This PR contains the changes required to boot the kernel on T2 per this LKML submission:
https://lore.kernel.org/asahi/20241201161942.36027-1-towinchenmi@gmail.com/T/#t
Overall T2 is similar to A10, and this takes care of the remaining:
P.S. T2 Boots on the P-core in Apple Fusion Architecture