First Commit

.gitignore

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+impl

README.md

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+# Nestang in Tang Nano 9k
+
+[Tang Nano 9k](https://github.com/hi631/tang-nano-9K) NES core written in System Verilog with [nestang](https://github.com/nand2mario/nestang) Dual Shock 2 Interface.
+
+Implemented for a [Tang Nano 9k](https://wiki.sipeed.com/hardware/en/tang/Tang-Nano-9K/Nano-9K.html) taking ~6.5k LUTs, and can be modified to have bluetooth gamepads by using [blueretro](https://github.com/darthcloud/BlueRetro) Project, if you want to do so, check out [docs](docs/) folder.
+
+![](docs/images/resources_utilization.png)
+
+Dualshock 2 (1 player) implementation of nestang in Tang Nano 9k

docs/README.md

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+# Documentation
+
+## Blueretro implementation
+
+Check out the Project [Constraint File](../src/NES_TN9.cst), but if you won't build from source or do any modifications you can make this wiring:
+
+| Tang Nano 9k | ESP32 | Dualshock 2 Interface |
+|:---:|:---:|:---:|
+|25|D33|CLOCK|
+|26|D32|COMMAND|
+|27|D19|DATA|
+|28|D34|ATTENTION|
+
+## ROM Flashing
+
+Just binary write the NES rom (in [iNES](https://www.nesdev.org/wiki/INES) format) into the microSD card in raw data.
+
+If you flash using [dd](https://en.wikipedia.org/wiki/Dd_%28Unix%29) command in linux, make sure the entire binary will fit 512 bytes block by padding the remaining space with any data.
+
+I recommend using a binary editor tool as [ImHex](https://github.com/WerWolv/ImHex) or make a script to do that job.
+
+## Build from Source
+
+Needs GoWin Official IDE, just:
+
+1. open the project [gprj](../nestang9k-ps2.gprj) file
+2. make the top entity to be `NES_TN9` module
+3. select `System Verilog 2007` to be the project synthesizer
+4. run Synthesize, then Place and Route tools
+5. flash the `.fs` file

nestang9k-ps2.gprj

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+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE gowin-fpga-project>
+<Project>
+    <Template>FPGA</Template>
+    <Version>5</Version>
+    <Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
+    <FileList>
+        <File path="src/DeltaSigmadac.v" type="file.verilog" enable="1"/>
+        <File path="src/MicroCode.v" type="file.verilog" enable="1"/>
+        <File path="src/NES_TN9.v" type="file.verilog" enable="1"/>
+        <File path="src/apu.v" type="file.verilog" enable="1"/>
+        <File path="src/compat.v" type="file.verilog" enable="1"/>
+        <File path="src/cpu.v" type="file.verilog" enable="1"/>
+        <File path="src/dualshock_controller.v" type="file.verilog" enable="1"/>
+        <File path="src/gowin_clkdiv/gowin_clkdiv.v" type="file.verilog" enable="1"/>
+        <File path="src/gowin_rpll/gowin_rpll.v" type="file.verilog" enable="1"/>
+        <File path="src/gowin_rpll/gowin_rpll2.v" type="file.verilog" enable="1"/>
+        <File path="src/gowin_sp/gowin_sp_2KBx8.v" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/audio_clock_regeneration_packet.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/audio_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/audio_sample_packet.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/auxiliary_video_information_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/hdmi.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/packet_assembler.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/packet_picker.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/serializer.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/source_product_description_info_frame.sv" type="file.verilog" enable="1"/>
+        <File path="src/hdmi+a/tmds_channel.sv" type="file.verilog" enable="1"/>
+        <File path="src/hq2x.v" type="file.verilog" enable="1"/>
+        <File path="src/hw_led.v" type="file.verilog" enable="1"/>
+        <File path="src/hw_uart.v" type="file.verilog" enable="1"/>
+        <File path="src/mmu.v" type="file.verilog" enable="1"/>
+        <File path="src/nes.v" type="file.verilog" enable="1"/>
+        <File path="src/ppu.v" type="file.verilog" enable="1"/>
+        <File path="src/psram_memory_interface_hs_2ch/psram_memory_interface_hs_WB16.v" type="file.verilog" enable="1"/>
+        <File path="src/rs232c_tx_rx.v" type="file.verilog" enable="1"/>
+        <File path="src/ukp2nes.v" type="file.verilog" enable="1"/>
+        <File path="src/ukprom.v" type="file.verilog" enable="1"/>
+        <File path="src/vga.v" type="file.verilog" enable="1"/>
+        <File path="src/sd_controller.vhd" type="file.vhdl" enable="1"/>
+        <File path="src/NES_TN9.cst" type="file.cst" enable="1"/>
+        <File path="src/gao/fpganes_vga.rao" type="file.gao" enable="0"/>
+    </FileList>
+</Project>

nestang9k-ps2.gprj.user

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+<?xml version="1" encoding="UTF-8"?>
+<!DOCTYPE ProjectUserData>
+<UserConfig>
+    <Version>1.0</Version>
+    <FlowState>
+        <Process ID="Synthesis" State="2"/>
+        <Process ID="Pnr" State="2"/>
+        <Process ID="Gao" State="2"/>
+        <Process ID="Rtl_Gao" State="2"/>
+    </FlowState>
+    <ResultFileList>
+        <ResultFile ResultFileType="RES.netlist" ResultFilePath="impl/gwsynthesis/nestang9k-ps2.vg"/>
+        <ResultFile ResultFileType="RES.pnr.bitstream" ResultFilePath="impl/pnr/nestang9k-ps2.fs"/>
+        <ResultFile ResultFileType="RES.pnr.pin.rpt" ResultFilePath="impl/pnr/nestang9k-ps2.pin.html"/>
+        <ResultFile ResultFileType="RES.pnr.posp.bin" ResultFilePath="impl/pnr/nestang9k-ps2.db"/>
+        <ResultFile ResultFileType="RES.pnr.pwr.rpt" ResultFilePath="impl/pnr/nestang9k-ps2.power.html"/>
+        <ResultFile ResultFileType="RES.pnr.report" ResultFilePath="impl/pnr/nestang9k-ps2.rpt.html"/>
+        <ResultFile ResultFileType="RES.pnr.timing.paths" ResultFilePath="impl/pnr/nestang9k-ps2.timing_paths"/>
+        <ResultFile ResultFileType="RES.pnr.timing.rpt" ResultFilePath="impl/pnr/nestang9k-ps2.tr.html"/>
+        <ResultFile ResultFileType="RES.syn.report" ResultFilePath="impl/gwsynthesis/nestang9k-ps2_syn.rpt.html"/>
+        <ResultFile ResultFileType="RES.syn.resource" ResultFilePath="impl/gwsynthesis/nestang9k-ps2_syn_rsc.xml"/>
+    </ResultFileList>
+    <Ui>000000ff00000001fd0000000200000000000002bc000005bcfc0200000002fc0000003e000005bc0000009901000017fa000000030100000005fb00000036004600700067006100500072006f006a006500630074002e00500061006e0065006c002e0048006900650072006100720063006800790100000000ffffffff0000007d00fffffffb0000002e004600700067006100500072006f006a006500630074002e00500061006e0065006c002e004900730073007500650100000000ffffffff000000d900fffffffb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000ffffffff0000004c00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff0000004d00fffffffb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00500072006f006300650073007301000000000000013e0000004c00fffffffc000000f5000002f30000000000fffffffa000000000100000001fb00000030004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00440065007300690067006e0100000000000001020000000000000000000000030000078000000094fc0100000001fc00000000000007800000000000fffffffa000000000100000001fb00000032004600700067006100500072006f006a006500630074002e00500061006e0065006c002e00470065006e006500720061006c0100000000ffffffff00000000000000000000073e000005bc00000004000000040000000800000008fc000000010000000200000004000000220043006f00720065002e0054006f006f006c006200610072002e00460069006c00650100000000ffffffff0000000000000000000000220043006f00720065002e0054006f006f006c006200610072002e004500640069007401000000b6ffffffff0000000000000000000000240043006f00720065002e0054006f006f006c006200610072002e0054006f006f006c00730100000195ffffffff0000000000000000ffffffff0100000264ffffffff0000000000000000</Ui>
+</UserConfig>

src/DeltaSigmadac.v

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+`define MSBI 15 // Most significant Bit of DAC input
+//This is a Delta-Sigma Digital to Analog Converter
+
+module audiodac(DACout, DACin, Clk, Reset);
+        output DACout; // This is the average output that feeds low pass filter
+        reg DACout; // for optimum performance, ensure that this ff is in IOB
+        input [`MSBI:0] DACin; // DAC input (excess 2**MSBI)
+        input Clk;
+        input Reset;
+
+        reg [`MSBI+2:0] DeltaAdder; // Output of Delta adder
+        reg [`MSBI+2:0] SigmaAdder; // Output of Sigma adder
+        reg [`MSBI+2:0] SigmaLatch; // Latches output of Sigma adder
+        reg [`MSBI+2:0] DeltaB; // B input of Delta adder
+
+        always @(SigmaLatch) DeltaB = {SigmaLatch[`MSBI+2], SigmaLatch[`MSBI+2]} << (`MSBI+1);
+        always @(DACin or DeltaB) DeltaAdder = DACin + DeltaB;
+        always @(DeltaAdder or SigmaLatch) SigmaAdder = DeltaAdder + SigmaLatch;
+        always @(posedge Clk or posedge Reset) begin
+                if(Reset) begin
+                        SigmaLatch <= 1'b1 << (`MSBI+1);
+                        DACout <= 1'b0;
+                end else begin
+                        SigmaLatch <= SigmaAdder;
+                        DACout <= SigmaLatch[`MSBI+2];
+                end
+        end
+endmodule