Change module names (#11)

* change module name when generating rtl

* clean up def.bzl

* remove bug prints

vitis/BUILD

@@ -19,3 +19,9 @@ cc_library(
     strip_include_prefix = "external/rules_hdl/",
     visibility = ["//visibility:public"],
 )
+
+py_binary(
+    name = "hls_generator",
+    srcs = ["hls_generator.py"],
+    visibility = ["//visibility:public"],
+)

vitis/defs.bzl

@@ -65,15 +65,19 @@ def _vitis_generate_impl(ctx):
         output = vitis_tcl,
         substitutions = substitutions,
     )
-
-    vitis_command = "source " + ctx.file.xilinx_env.path + " && "
+    args = []
+    args.append("--vitis_tcl")
+    args.append(vitis_tcl.path)
+    args.append("--vitis_log")
+    args.append(vitis_log.path)
+    args.append("--outputs")
+    args.append(ctx.outputs.out.path)
+    args.append("--label")
+    args.append(ctx.label.name)
+    args.append("--xilinx_env")
+    args.append(ctx.file.xilinx_env.path)
     if ctx.attr.use_vivado_hls:
-        vitis_command += "vivado_hls " + vitis_tcl.path
-    else:
-        vitis_command += "vitis_hls " + vitis_tcl.path
-    vitis_command += " -l " + vitis_log.path
-    vitis_command += " && tar -czvf " + ctx.outputs.out.path + " -C "
-    vitis_command += ctx.label.name + "/sol1/impl/verilog ."
+        args.append("--use_vivado_hls")
 
     outputs = [vitis_log, ctx.outputs.out]
 
@@ -82,11 +86,12 @@ def _vitis_generate_impl(ctx):
     else:
         progress_message = "Running with vitis_hls: {}".format(ctx.label.name)
 
-    ctx.actions.run_shell(
+    ctx.actions.run(
         outputs = outputs,
         inputs = all_files + [vitis_tcl, ctx.file.xilinx_env],
+        arguments = args,
         progress_message = progress_message,
-        command = vitis_command,
+        executable = ctx.executable._run_hls_gen,
     )
 
     return [
@@ -107,6 +112,12 @@ vitis_generate = rule(
             default = "@rules_hdl//vitis:vitis_generate.tcl.template",
             allow_single_file = [".template"],
         ),
+        "_run_hls_gen": attr.label(
+            doc = "Tool used to run hls generator.",
+            executable = True,
+            cfg = "exec",
+            default = ":hls_generator",
+        ),
         "xilinx_env": attr.label(
             doc = "Environment variables for xilinx tools.",
             allow_single_file = [".sh"],

vitis/hls_generator.py

@@ -0,0 +1,141 @@
+import argparse
+import os
+import logging
+import subprocess
+import re
+import tarfile
+
+
+logger = logging.getLogger(__name__)
+
+logging_levels = {
+    "critical": logging.CRITICAL,
+    "error": logging.ERROR,
+    "warn": logging.WARNING,
+    "warning": logging.WARNING,
+    "info": logging.INFO,
+    "debug": logging.DEBUG,
+}
+
+
+def parse_args():
+    parser = argparse.ArgumentParser()
+    parser.add_argument(
+        "--vitis_tcl",
+        type=str,
+        required=True,
+        help="The path to the vitis tcl",
+    )
+    parser.add_argument(
+        "--vitis_log",
+        type=str,
+        required=True,
+        help="The path to the vitis log",
+    )
+    parser.add_argument(
+        "--outputs",
+        type=str,
+        required=True,
+        help="The path to the outputs",
+    )
+    parser.add_argument(
+        "--label",
+        type=str,
+        required=True,
+        help="The label name",
+    )
+    parser.add_argument(
+        "--xilinx_env",
+        type=str,
+        required=True,
+        help="The path to the xilinx_env.",
+    )
+    parser.add_argument(
+        "--use_vivado_hls",
+        type=bool,
+        default=False,
+        help="If use vivado hls",
+    )
+    parser.add_argument(
+        "-l",
+        "--log_level",
+        default="debug",
+        choices=logging_levels.keys(),
+        help="The logging level to use.",
+    )
+    return parser.parse_args()
+
+
+def send_command(command):
+    build_process = subprocess.Popen(
+        "/bin/bash", stdin=subprocess.PIPE, stdout=subprocess.PIPE
+    )
+    out, err = build_process.communicate(command.encode("utf-8"))
+    logger.info(out.decode("utf-8"))
+    if err:
+        logger.error(err.decode("utf-8"))
+
+
+def replace_module_names(verilog_files, verilog_files_dir, top_name):
+    module_pattern = re.compile(r"(?<=^module\s).\S+", re.IGNORECASE)
+    module_names_to_change = []
+    data_to_write = {}
+    # Read files and find module names.
+    for verilog_file in verilog_files:
+        full_path = os.path.join(verilog_files_dir, verilog_file)
+        with open(full_path, "r") as f:
+            data_to_write[full_path] = f.readlines()
+            for line in data_to_write[full_path]:
+                module_name = module_pattern.findall(line)
+                # Keep the top level name.
+                if module_name and module_name[0] != top_name:
+                    module_names_to_change += module_name
+    # replace file contents
+    for verilog_file in verilog_files:
+        full_path = os.path.join(verilog_files_dir, verilog_file)
+        this_data = data_to_write[full_path]
+        for i in range(len(this_data)):
+            for module_name_to_change in module_names_to_change:
+                this_data[i] = re.sub(
+                    r"\b{module_name}\b".format(module_name=module_name_to_change),
+                    f"{module_name_to_change}_{top_name}",
+                    this_data[i],
+                )
+
+    for verilog_file in verilog_files:
+        full_path = os.path.join(verilog_files_dir, verilog_file)
+        this_data = data_to_write[full_path]
+        with open(full_path, "w") as f:
+            for line in this_data:
+                f.write(line)
+
+
+def main():
+    args = parse_args()
+    # TODO(cruxml-bopeng): Move this to utils_logging.
+    logging.basicConfig(
+        format="%(asctime)s,%(msecs)d %(levelname)-8s [%(filename)s:%(lineno)d] %(message)s",
+        datefmt="%Y-%m-%d:%H:%M:%S",
+        level=logging_levels[args.log_level],
+    )
+
+    if args.use_vivado_hls:
+        builder_name = "vivado_hls"
+    else:
+        builder_name = "vitis_hls"
+    build_commands = (
+        f"source {args.xilinx_env}; {builder_name} {args.vitis_tcl} -l {args.vitis_log}"
+    )
+    send_command(build_commands)
+    verilog_files_dir = os.path.join(args.label, "sol1/impl/verilog")
+    verilog_files = os.listdir(verilog_files_dir)
+    replace_module_names(verilog_files, verilog_files_dir, args.label)
+    # Writ files
+    with tarfile.open(args.outputs, "w:gz") as tar:
+        for verilog_file in verilog_files:
+            full_path = os.path.join(verilog_files_dir, verilog_file)
+            tar.add(full_path, arcname=os.path.basename(full_path))
+
+
+if __name__ == "__main__":
+    main()

vitis/tests/BUILD

@@ -1,4 +1,6 @@
 load("//vitis:defs.bzl", "vitis_generate")
+load("//verilog:providers.bzl", "verilog_library")
+load("//verilator:defs.bzl", "verilator_cc_library")
 
 # This is to test the path of generated headers.
 genrule(
@@ -88,3 +90,36 @@ vitis_generate(
     xilinx_env = ":xilinx_env_vivado.sh",
     deps = [":hls_adder_vivado"],
 )
+
+verilog_library(
+    name = "adder_top",
+    srcs = glob(["adder_top/*"]),
+    visibility = ["//:__subpackages__"],
+)
+
+verilator_cc_library(
+    name = "adder_verilator",
+    module = "adder_top",
+    module_top = "adder",
+    vopts = [
+        # Ignore the delay time warning.
+        "-Wno-STMTDLY",
+        # Ignore the bit width mistmatch warning.
+        "-Wno-WIDTH",
+        # Ignore the unused signal warning.
+        "-Wno-UNUSED",
+    ],
+)
+
+cc_test(
+    name = "adder_verilator_test",
+    srcs = [
+        "adder_verilator_test.cc",
+    ],
+    deps = [
+        "adder_verilator",
+        "hls_adder",
+        "@com_google_googletest//:gtest",
+        "@com_google_googletest//:gtest_main",
+    ],
+)