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Setup a new Sinara system

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Roy Ready edited this page Mar 17, 2023 · 9 revisions

This page describes how to set up a new Sinara system.

  • Make sure the system's hardware is connected correctly (EEM ports, clock connections) and get a json file corresponding to the system connections. For a M-labs supported system, the file might be in https://git.m-labs.hk/M-Labs/sinara-systems-legacy, or the file can be edited based on other json configuration files.

  • Connect the Sinara system with DC power, ethernet, and external clock if applicable. I think external clock needs to be applied before the DC power. Find the ip address and change the ip address if needed (see manual).

  • Setup the software per steps in the lab wiki.

  • Download or compile the gateware for kasli.

We no longer use conda, the gateware website does not exist

If the system is supported by M-labs, likely a command conda install artiq-board-kasli-ucsb would work. This will download a gateware corresponding to latest M-labs master code. ucsb should be replaced by the variant name, found as the filename in https://git.m-labs.hk/M-Labs/sinara-systems/src/branch/master.

Copy the entire board-support folder from .../anaconda3/envs/artiq/Lib/site-packages/artiq to C:\Users\scientist\code\artiq\artiq. If compiling, follow https://forum.m-labs.hk/d/75-configuring-a-custom-kalsi-crate. You need to substitute the files in the board-support folder with the same files in the compiled folder.

Flash the kasli with the new gateware (see manual). If the firmware was copied to C:\Users\scientist\code\artiq\artiq, it can be deleted after flashing.

M-Labs tests and flashes the firmware to the latest stable ARTIQ release, so we don't have to flash unless custom/beta firmware is desired.

  • Generate a device_db.py file from the json configuration file. This file can be generated automatically with python -m artiq.frontend.artiq_ddb_template your_variant.json -o device_db.py. The device_db.py file should be placed in the folder that artiq_master runs in.

  • After all connections are made, try to ping 192.168.1.75 (Default sinara system IP) from the control computer. If this can be successfully done, the computer and the hardware are connected to the same network. Follow the ARTIQ manual to change the hardware IP to a different address. currently

  • 192.168.1.77 is used for d7

  • 192.168.1.78 is used for forge

  • 192.168.1.80 is used for Enterprise

192.168.1.76 was used for enterprise on the for the old box, Dip is now prototyping on this

Change the IP address in device_db.py accordingly. Update this wiki page when setting up new hardware.

Changing a TTL bank between output and input

TODO

Setting up external clock for a kasli

We can use a 125 MHz clock for the kasli. If the DDSes gets the clock directly from the kasli (default), no hardware change inside of the kasli box is needed. However, the json file, and therefore the gateware and the devices.py file need to be changed.

  • Add a "ext_ref_frequency": 125e6, line in the base object of the json file.
  • Recompile the gateware (or contact M-Labs to get it if the setup is supported by them).
  • Flash the kasli with the new gateware.
  • Generate devices.py and replace the old one.

Use Docker to build firmware

Nix installation in ubuntu docker: See https://github.com/OdysLam/ddapptools/blob/main/docker/Dockerfile

Shares host files with a docker container (useful for sharing installation file of Xilinx Vivado): https://stackoverflow.com/a/24641998/4696323

Current version of Vivado used by m-labs is 2021.1 (See https://git.m-labs.hk/M-Labs/nix-scripts/src/branch/master/artiq-fast/vivado.nix)

Firmware building with Kasli-SoC

https://git.m-labs.hk/M-Labs/artiq-zynq

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