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@KULeuven-MICAS

MICAS (KU Leuven)

We initiate, drive and realize breakthroughs in micro and nano-electronic systems, for a better and more comfortable life for everyone.
README.md

This is the GitHub organization for the MICAS research group at KU Leuven. Here you can find open-source projects made by us and our collaborators.

SNAX Framework

Snax is an end-to-end, open-source multi-accelerator cluster design framework. It consists of the snax-mlir compile toolchain and the snax cluster hardware framework.

SNAX-MLIR Repo

SNAX Cluster Repo

HeMAiA Repo

Fast DNN Accelerator Design Space Exploration Frameworks

ZigZag Repo | Documentation | Tutorial

ZigZag targets rapid DSE for DNN accelerator platforms supporting an broad set of hardware architectures and workload scheduling scenarios beyond other existing frameworks.
The latest version of ZigZag includes support for modeling of analog and digital in-memory computing accelerators and estimating both peak/workload performance at the macro and system level.

Stream Repo | Documentation | Tutorial

Stream is an extension of ZigZag capable of modeling multi-core DNN acceleration employing fine-grained layer-fused processing.

ZigZag-LLM Repo

ZigZag-LLM is a framework to rapidly model Large Language Models on dedicated, single-core accelerators and facilitates early identification of energy bottlenecks within the hardware architecture.

DeFiNes Repo

DeFiNes extends ZigZag to enable the DSE of cross-layer depth-first scheduling (a.k.a. layer fusion, or cascaded execution)

Accelerator-aware Neural Network Deployment

HTVM Repo

HTVM is a neural network compiler based on Dory and TVM that allows for efficient neural network deployment on heterogenous TinyML platforms with scratchpad-memory accelerators.

Artificial Intelligence System on Chips (SoCs)

TinyVers Repo

V. Jain, S. Giraldo, J. D. Roose, L. Mei, B. Boons and M. Verhelst, "TinyVers: A Tiny Versatile System-on-Chip With State-Retentive eMRAM for ML Inference at the Extreme Edge," in IEEE Journal of Solid-State Circuits, doi: 10.1109/JSSC.2023.3236566.

V. Jain, S. Giraldo, J. D. Roose, B. Boons, L. Mei and M. Verhelst, "TinyVers: A 0.8-17 TOPS/W, 1.7 μW-20 mW, Tiny Versatile System-on-chip with State-Retentive eMRAM for Machine Learning Inference at the Extreme Edge," 2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2022, pp. 20-21, doi: 10.1109/VLSITechnologyandCir46769.2022.9830409.

DIANA Repo: It is coming

K. Ueyoshi et al., "DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC," 2022 IEEE International Solid- State Circuits Conference (ISSCC), San Francisco, CA, USA, 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731716.

P. Houshmand et al., "DIANA: An End-to-End Hybrid DIgital and ANAlog Neural Network SoC for the Edge," in IEEE Journal of Solid-State Circuits, vol. 58, no. 1, pp. 203-215, Jan. 2023, doi: 10.1109/JSSC.2022.3214064.

DPU Repo

N. Shah, L. I. G. Olascoaga, S. Zhao, W. Meert and M. Verhelst, "DPU: DAG Processing Unit for Irregular Graphs With Precision-Scalable Posit Arithmetic in 28 nm," in IEEE Journal of Solid-State Circuits, vol. 57, no. 8, pp. 2586-2596, Aug. 2022, doi: 10.1109/JSSC.2021.3134897.

DPU-v2 Repo

NN. Shah, W. Meert and M. Verhelst, "DPU-v2: Energy-efficient execution of irregular directed acyclic graphs," 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO), Chicago, IL, USA, 2022, pp. 1288-1307, doi: 10.1109/MICRO56248.2022.00090.



Pinned Loading

  1. zigzag zigzag Public

    HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

    C++ 120 44

  2. stream stream Public

    Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.

    Python 46 20

  3. htvm htvm Public

    Efficient Neural Network Deployment on Heterogenous TinyML Platforms

    Python 14

  4. snax_cluster snax_cluster Public

    Forked from pulp-platform/snitch_cluster

    A heterogeneous accelerator-centric compute cluster

    SystemVerilog 12 10

  5. snax-mlir snax-mlir Public

    Driving Snax with MLIR

    Python 13 4

  6. zigzag-llm zigzag-llm Public

    Model LLM inference on single-core hardware architectures

    Python 4

Repositories

Showing 10 of 37 repositories
  • zigzag Public

    HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators

    KULeuven-MICAS/zigzag’s past year of commit activity
    C++ 120 MIT 44 9 1 Updated Dec 26, 2024
  • snax_cluster Public Forked from pulp-platform/snitch_cluster

    A heterogeneous accelerator-centric compute cluster

    KULeuven-MICAS/snax_cluster’s past year of commit activity
    SystemVerilog 12 Apache-2.0 58 17 (3 issues need help) 8 Updated Dec 25, 2024
  • stream Public

    Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.

    KULeuven-MICAS/stream’s past year of commit activity
    Python 46 MIT 20 3 3 Updated Dec 24, 2024
  • snax_cgra Public
    KULeuven-MICAS/snax_cgra’s past year of commit activity
    SystemVerilog 0 0 0 0 Updated Dec 24, 2024
  • snax-mlir Public

    Driving Snax with MLIR

    KULeuven-MICAS/snax-mlir’s past year of commit activity
    Python 13 4 3 11 Updated Dec 20, 2024
  • llvm-build Public

    Some prebuilt compiler toolchains for the SNAX ecosystem

    KULeuven-MICAS/llvm-build’s past year of commit activity
    Shell 0 0 0 0 Updated Dec 17, 2024
  • vcd-to-csv Public

    Generate csv files from a clocked vcd trace

    KULeuven-MICAS/vcd-to-csv’s past year of commit activity
    Rust 1 0 0 0 Updated Dec 16, 2024
  • hypercorex Public
    KULeuven-MICAS/hypercorex’s past year of commit activity
    SystemVerilog 0 Apache-2.0 0 0 0 Updated Dec 15, 2024
  • HeMAiA Public Forked from pulp-platform/occamy

    The warm and cozy house for SNAX Cluster 🏠

    KULeuven-MICAS/HeMAiA’s past year of commit activity
    Tcl 1 Apache-2.0 13 3 1 Updated Dec 12, 2024
  • hemaia_axi_spi_slave Public Forked from pulp-platform/axi_spi_slave
    KULeuven-MICAS/hemaia_axi_spi_slave’s past year of commit activity
    SystemVerilog 0 33 0 1 Updated Dec 12, 2024
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