RTL code of Error detection capable Montgomery Ladder over curve 448 in "Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder".
Module hierarchy is as follow:

• Iterator.sv
  • Montgomery_step.sv
    • core.sv
      • adder.sv (Modular Addition)
      • speed_mult_red (Modular Multiplication)
• Error_detection.sv

citation

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@ARTICLE{10587011,
  author={Ahmadi, Kasra and Aghapour, Saeed and Kermani, Mehran Mozaffari and Azarderakhsh, Reza},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, 
  title={Efficient Error Detection Cryptographic Architectures Benchmarked on FPGAs for Montgomery Ladder}, 
  year={2024},
  volume={},
  number={},
  pages={1-0},
  keywords={Binary trees;Field programmable gate arrays;Elliptic curves;Hardware;Cryptography;Clocks;Software;ARM processor;fault detection;field-programmable gate array (FPGA);Montgomery Ladder;reliability},
  doi={10.1109/TVLSI.2024.3419700}}