pci-bus: Support MSI & MSI-X interrupts

- MSI-X state sits in a dedicated BAR (BAR4 or BAR5, whichever is available). If MSI-X state can't be assigned a BAR, only MSI support is reported for a function
- Implement vector masking & pending bits properly
- Do not send MSI/MSI-X if Bus Mastering is disabled
- Currently only 1 MSI-X entry is reported. This is because NVMe implementation doesn't yet deal with multiple MSI vectors properly yet, so it needs additional fixes