Update README.md

MattiaDif · Jun 8, 2024 · cedae5c · cedae5c
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@@ -12,6 +12,4 @@ The SPI has been validated for an FPGA architecture running at 100MHz, and it ha
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 ### NOTES
-The current state of the work provides VHDL code. I'm planning to upload the Verilog version. 
-
 To contribute refers to the *dev* branch! Thanks and see you around! :)