REF NIC
###Intro
The NIC (Network Interface Card) reference design provides a set of board-specific projects.
This design should be considered as the most fundamental application when using ONetSwitch for network innovation, who sets up a Linux host on the board with all the GE ports as its NICs, by implementing a PHY-MAC-DMA sequence.
Demo runs at Linux level.
###Features
| Feature | Description |
|---|---|
| Network STD. | IEEE 802.3, IEEE 802.3u, IEEE 802.3ab |
| Physical Layer | 1. 1000/100/10Mbps Copper RJ45 |
| 2. support Auto MDIX, support Auto Neg. | |
| DataLink Layer | 1. RGMII(ONS45 ONS20)/SGMII(ONS30) |
| 2. support Promiscuous Mode (default Non-Promiscuous) | |
| 3. support MDIO management to all PHYs |
###Project List
| Board | Project |
|---|---|
| ONetSwitch20 | ons20-app11-ref_nic |
| ONetSwitch30 | ons30-app11-ref_nic |
| ONetSwitch45 | ons45-app11-ref_nic |
###Pre-Built Images
- For quick start demo.
| File | ONetSwitch20 | ONetSwitch30 | ONetSwitch45 |
|---|---|---|---|
| boot.bin | Download |
Download |
Download |
| devicetree | Download |
Download |
Download |
| kernel | Download |
Download |
Download |
| rootfs (EXT) | Download |
Download |
Download |
| sw-lib | N/A |
N/A |
N/A |
| sw-app | N/A |
N/A |
N/A |
- For image assembling.
| File | ONetSwitch20 | ONetSwitch30 | ONetSwitch45 |
|---|---|---|---|
| system.bit | Download |
Download |
Download |
| dt source | Download |
Download |
Download |
| fsbl | Download |
Download |
Download |
| u-boot (FAT) | Download |
Download |
Download |
| u-boot (EXT) | Download |
Download |
Download |
| rootfs (FAT) | Download |
Download |
Download |
###Block Diagram
###Design Outline
####Clocks
| Freq. | Description |
|---|---|
| 125MHz | PS FCLK0. Main clock for data path, especially the AXI4-Stream. |
| 75MHz | PS FCLK1. Main clock for control i/f, especially the AXI4-Lite. |
| 200MHz | PS FCLK2. Aux. clock for delay ctrl in ONS20/ONS45 RGMII. |
| 125MHz(LVDS) | For ONS30 ONLY, from AD9516-3 driving SGMII PCS/PMA. |
####Resets
The system reset is from Processor System Reset Module and synchronized with the slowest clock, normally the 75MHz PS FCLK1.
The reset to AXI4-Stream i/f for DMA-MAC pairs is generated by each DMA.
####Interrupts
Total 12.
One interrupts per AXI Ethernet i.e. MAC;
Two interrupts per AXI DMA, each for DMA MM2S and DMA S2MM.
####Core Design
The core module in this case is the four pairs of DMA-MAC binding, each of the four is an NIC.
Taking care of the dual channel AXI4-Stream for separated data/ctrl streams would be enough to finish the design. Refer to IP user guides for more detail about the dual-channel.
Notice also the driver and devicetree adaptation for 1-to-4 MDIO management and DMA-MAC binding, originally it's 1-to-1.
###Address Map
For Zynq PS address map, please refer to Appx. B of Xilinx UG585.
For MAC and DMA register offset and description, please refer to Xilinx PG138 and Xilinx PG021.
| ONS20/30/45 | BaseAddr | Notes |
|---|---|---|
| axi_dma0 | 0x40400000 | |
| axi_dma1 | 0x40410000 | |
| axi_dma2 | 0x40420000 | |
| axi_dma3 | 0x40430000 | |
| axi_ethernet0 | 0x43c00000 | eth1, MDIO master |
| axi_ethernet1 | 0x43c40000 | eth2 |
| axi_ethernet2 | 0x43c80000 | eth3 |
| axi_ethernet3 | 0x43cc0000 | eth4 |
###Demo
- Prepare the images in SD/TF card, or download the pre-built ones.
- Try some Linux commands to configure the NIC, e.g. ifconfig
- Try some network commands to do something, e.g. ping