ETDSPC-01
ETDSPC aims to give the students insight into system de# FPGAs. By combining custom hardware written in VHDL with a microprocessor, we can achieve high flexibility, high performance and a small footprint. The students will be trained in designing and implementing feasible designs. In addition, the students will learn methods for testing these designs.
When the course is completed, the students are expected to be able to:
- Implement programs for FPGAs, written in VHDL
- Use ModelSim and test benches to simulate VHDL designs
- Explain the concepts: clock domains, clock skew, pipelining, PLL and memory components
- Use soft cores to build an SoC (System On Chip) system
- Implement C programs to run on SoC
- Implement signal processing algorithms in VHDL
- Repetition of basic VHDL concepts
- Test benches and assertions
- Application of memory components in FPGA
- Design Constraints
- Clocks and Timing
- IP functions (Mega Wizard)
- SOPC Builder (system generation)
- NIOS II Soft processor
- NIOS II programming – the core
- Altera FPGA architecture
- Application of signal processing algorithms in VHDL
- Ongoing project exercises