verilog-alu-qupj-Flow Summary.csv

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Flow Summary

Flow Status,Successful - Wed Nov 27 22:23:52 2019
Quartus II 64-Bit Version,15.0.0 Build 145 04/22/2015 SJ Full Version
Revision Name,verilog-alu-qupj
Top-level Entity Name,verilog-alu-qupj-block
Family,Arria II GZ
Logic utilization,< 1 %
    Combinational ALUTs,"63 / 179,200 ( < 1 % )"
    Memory ALUTs,"0 / 89,600 ( 0 % )"
    Dedicated logic registers,"0 / 179,200 ( 0 % )"
Total registers,0
Total pins,100 / 634 ( 16 % )
Total virtual pins,0
Total block memory bits,"0 / 11,381,760 ( 0 % )"
DSP block 18-bit elements,0 / 800 ( 0 % )
Total GXB Receiver Channel PCS,0 / 16 ( 0 % )
Total GXB Receiver Channel PMA,0 / 16 ( 0 % )
Total GXB Transmitter Channel PCS,0 / 16 ( 0 % )
Total GXB Transmitter Channel PMA,0 / 16 ( 0 % )
Total PLLs,0 / 6 ( 0 % )
Total DLLs,0 / 4 ( 0 % )
Device,EP2AGZ225FF35I3
Timing Models,Final