verilog-alu

build

$ make

$ gtkwave ./hoge.vcd

Name		Name	Last commit message	Last commit date
Latest commit History 81 Commits
db		db
images		images
incremental_db		incremental_db
library		library
output_files		output_files
simulation/modelsim		simulation/modelsim
test		test
verilog-alu-qupj-Flow Summary.htm_files		verilog-alu-qupj-Flow Summary.htm_files
.gitignore		.gitignore
IMG_20191015_105502.jpg		IMG_20191015_105502.jpg
IMG_20191015_115107.jpg		IMG_20191015_115107.jpg
Makefile		Makefile
README.md		README.md
alu1.pdf		alu1.pdf
alu_16bit.v		alu_16bit.v
alu_1bit.v		alu_1bit.v
alu_32bit.v		alu_32bit.v
alu_8bit.v		alu_8bit.v
decoder.pdf		decoder.pdf
serv_req_info.txt		serv_req_info.txt
verilog-alu-qupj-Flow Summary.csv		verilog-alu-qupj-Flow Summary.csv
verilog-alu-qupj-Flow Summary.htm		verilog-alu-qupj-Flow Summary.htm
verilog-alu-qupj-Flow Summary.rpt		verilog-alu-qupj-Flow Summary.rpt
verilog-alu-qupj-block.bdf		verilog-alu-qupj-block.bdf
verilog-alu-qupj.qpf		verilog-alu-qupj.qpf
verilog-alu-qupj.qsf		verilog-alu-qupj.qsf
verilog-alu-qupj.qws		verilog-alu-qupj.qws
verilog-alu-qupj.tis_db_list.ddb		verilog-alu-qupj.tis_db_list.ddb