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1. OpenABC OpenABC Public

   OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph level prediction problems in chip design.

   Verilog 128 21

2. ABC-RL ABC-RL Public

   This is work-in-progress (WIP) refactored implementation of "Retreival-guided Reinforcement Learning for Boolean Circuit Minimization" work published in ICLR 2024.

   Verilog 5 1

3. robust-pnr-time robust-pnr-time Public

   Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"

   Verilog 5 2

4. ALMOST ALMOST Public

   ALMOST: Adversarial Learning to Mitigate Oracle-less ML Logic Locking Attacks via Synthesis Tuning

   Verilog 2