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Projects Ideas List
Over time the NetFPGA (and NetFPGA SUME in particular) project has built a list of ideas for contributed projects that can be useful, but no hands are available to do it. If you would like to contribute a NetFPGA project, you might pursue this list to get a sense of the kinds of work available to do. Contributions are not limited to this list!
Please do contact us before starting on it though - sometimes items remain on the list after they are completed.
Decription: The CPLD is used in the NetFPGA-SUME board to provide a fast programming interface from 2 FLASH devices to the FPGA. It uses SlaveMap interface. The CPLD designed by Digilent and providing the interface is not open-source. The goal of this project is to design a CPLD that will provide the same functionality and will be open-source.
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
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Experience in CPLD design
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Verilog/VHDL knowledge
Decription: A CPLD is used in the NetFPGA-SUME board to provide a fast programming interface from 2 FLASH devices to the FPGA. It uses SlaveMap interface and the FLASH can not be directly programmed using JTAG / Xilinx's tools. Currently, a dedicated (closed-source) Digilent solution is used for FLASH programming. The goal of this project is two fold: 1. Design a small (verilog) module, to be included in all NetFPGA SUME projects, which allows access to the FLASH 2. Design a software to run on top of the host and program the FLASH through the FPGA (using the above module).
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
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Verilog knowledge
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C knowledge
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Experience in FLASH programming - optional
Decription: A simple OpenFlow switch project, possibly a port from previous platforms.
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
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Verilog knowledge
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OpenFlow knowledge - recommended
Decription: The reference designs are using small BRAM based output queues. The goal of this project is to write a SRAM based output queues module, that can provide maximum throughput.
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
- Verilog knowledge
Decription: The reference designs are using small BRAM based output queues. The goal of this project is to write a SRAM based output queues module, that can provide maximum buffering (i.e. support a huge number of buffers).
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
- Verilog knowledge
Decription: Full reconfiguration of the board typically requires a reset cycle of the machine, e.g. for PCIe enumeration. The goal of this project is to enable partial reconfiguration of the NetFPGA SUME platform, e.g. without the PCIe and DMA engines or of the datapath only.
Technical contact: NetFPGA Dev team, Cambridge
Requirements:
- Advanced knowledge of Vivado