Verilog implementations of fundamental combinational and sequential circuits (with testbenches)
Starting out with Verilog during my first digital systems design class, I couldn't find a comprehensive Verilog guide with multiple examples all in one resource. So I decided to create this reference repository consolidating all my Verilog code as I progressed in class and my own study. It includes the dataflow, structural, and behavioral modeling of Verilog code for a broad range of fundamental combinational and sequential circuits, complete with corresponding testbenches
- Half Adder
- Full Adder
- Half Subtractor
- Full Subtractor
- 4-bit Ripple Carry Adder, n-Bit
- Combined Parallel Adder/Subtractor
- Carry Look-Ahead Adder
- Decoder (2:4)
- Decoder (3:8)
- Encoder (4:2)
- Encoder (Octal:Binary)
- Priority Encoder (4:2)
- Multiplexer (4:1)
- Demultiplexer (1:8)
- Parity Generator
- Parity Checker
- Array Multiplier
- Booth Multiplier
- LUT Multiplier
- LUT Multiplier py code generator
- Booth Algorithm 4-bit
- Basic Gates
- Magnitude Comparator
- Binary to Gray Code
- Gray Code to Binary
- Tri-State Buffers
- Sign-Extender(9 to 16)
- Switch-Level-Modeled Basic Gates
- Reversible Full Adder
- SR Latch
- D Latch
- SR Flip-FLop
- D Flip-Flop
- JK Flip-Flop
- T Flip-Flop
- SISO
- SIPO
- PISO
- PIPO
- Asynchronous Counter
- Synchronous Counter
- Ring Counter
- Johnson Counter
- Gray Counter
- FSM Examples
- Moore Sequence Detector
- Mealy Sequence Detector
• Boolean Expression → Dataflow
• Logic Diagram → Structural
• Truth Table → Behavioral
EDAPlayground is an application that includes an online IDE to simulate Verilog programs and a community project hub
• Compiler: Icarus Verilog 0.9.7
• To open EPWave after run, include the lines $dumpfile("dump.vcd"); $dumpvars; at the start of the testbenches' inital block
