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submodule: bump CoupledL2
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@sumailyyc
sumailyyc committed Sep 28, 2024
1 parent d419211 commit 13bc4ab
Showing 1 changed file with 1 addition and 1 deletion.
2 changes: 1 addition & 1 deletion coupledL2
Submodule coupledL2 updated 38 files
+1 −1 HuanCun
+2 −0 src/main/scala/coupledL2/BaseSlice.scala
+58 −0 src/main/scala/coupledL2/Common.scala
+25 −2 src/main/scala/coupledL2/CoupledL2.scala
+22 −13 src/main/scala/coupledL2/DataStorage.scala
+9 −1 src/main/scala/coupledL2/Directory.scala
+23 −5 src/main/scala/coupledL2/GrantBuffer.scala
+2 −0 src/main/scala/coupledL2/L2Param.scala
+2 −2 src/main/scala/coupledL2/MSHRBuffer.scala
+13 −5 src/main/scala/coupledL2/RequestArb.scala
+2 −2 src/main/scala/coupledL2/SinkC.scala
+74 −0 src/main/scala/coupledL2/SinkCMO.scala
+6 −5 src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala
+1 −1 src/main/scala/coupledL2/prefetch/Prefetcher.scala
+16 −15 src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala
+8 −0 src/main/scala/coupledL2/tl2chi/Bundle.scala
+16 −42 src/main/scala/coupledL2/tl2chi/MMIOBridge.scala
+78 −46 src/main/scala/coupledL2/tl2chi/MSHR.scala
+9 −102 src/main/scala/coupledL2/tl2chi/MSHRCtl.scala
+55 −12 src/main/scala/coupledL2/tl2chi/MainPipe.scala
+1 −0 src/main/scala/coupledL2/tl2chi/RXDAT.scala
+1 −0 src/main/scala/coupledL2/tl2chi/RXRSP.scala
+4 −3 src/main/scala/coupledL2/tl2chi/RXSNP.scala
+8 −4 src/main/scala/coupledL2/tl2chi/Slice.scala
+63 −28 src/main/scala/coupledL2/tl2chi/TL2CHICoupledL2.scala
+18 −5 src/main/scala/coupledL2/tl2chi/TXDAT.scala
+21 −17 src/main/scala/coupledL2/tl2chi/chi/AsyncBridge.scala
+25 −5 src/main/scala/coupledL2/tl2chi/chi/LinkLayer.scala
+2 −1 src/main/scala/coupledL2/tl2chi/chi/NetworkLayer.scala
+16 −3 src/main/scala/coupledL2/tl2tl/MainPipe.scala
+2 −19 src/main/scala/coupledL2/tl2tl/SinkB.scala
+4 −0 src/main/scala/coupledL2/tl2tl/Slice.scala
+16 −4 src/main/scala/coupledL2/tl2tl/SourceC.scala
+19 −2 src/main/scala/coupledL2/utils/BankedSRAM.scala
+215 −0 src/main/scala/coupledL2/utils/Queue_SRAM.scala
+115 −0 src/main/scala/coupledL2/utils/SplittedSRAM.scala
+72 −0 src/test/scala/TestSplittedSRAM.scala
+10 −10 src/test/scala/chi/TestTop.scala

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