chore(TestTop): replace DummyLLC with OpenLLC + OpenNCB in TestTopSoC (…

…#16)
OpenXiangShan · Oct 25, 2024 · 193d054 · 193d054
1 parent daab43f
commit 193d054
Showing 1 changed file with 33 additions and 3 deletions.
diff --git a/src/test/scala/TestTop.scala b/src/test/scala/TestTop.scala
@@ -11,6 +11,7 @@ import freechips.rocketchip.tilelink._
 import org.chipsalliance.cde.config._
 import coupledL2._
 import coupledL2.tl2chi._
+import cc.xiangshan.openncb._
 import utility._
 
 class TestTop_L3()(implicit p: Parameters) extends LazyModule with HasCHIMsgParameters {
@@ -113,9 +114,17 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1)(implic
     )
   }))))
 
-  val l3 = LazyModule(new DummyLLC(numCores)(p.alter((_, _, _) => {
+  val l3Bridge = LazyModule(new OpenNCB()(new Config((site, here, up) => {
     case CHIIssue => "B"
+    case NCBParametersKey => new NCBParameters(
+      axiMasterOrder      = EnumAXIMasterOrder.WriteAddress,
+      readCompDMT         = false,
+      writeCancelable     = false,
+      writeNoError        = true,
+      axiBurstAlwaysIncr  = true
+    )
   })))
+
   val ram = LazyModule(new AXI4RAM(AddressSet(0, 0xff_ffffL), beatBytes = 32))
 
   val bankBinders = (0 until numCores).map(_ => BankBinder(banks, 64))
@@ -155,7 +164,7 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1)(implic
   ram.node := 
     AXI4Xbar() :=
     AXI4Fragmenter() :=
-    l3.axi4node
+    l3Bridge.axi4node
 
   lazy val module = new LazyModuleImp(this) {
     val timer = WireDefault(0.U(64.W))
@@ -180,15 +189,36 @@ class TestTopSoC(numCores: Int = 1, numULAgents: Int = 0, banks: Int = 1)(implic
       }
     }
 
+    val l3 = Module(new OpenLLC()(new Config((site, here, up) => {
+      case CHIIssue => "B"
+      case OpenLLCParamKey => OpenLLCParam(
+        clientCaches = Seq.fill(numCores)(cacheParams.copy(
+          ways = 2,
+          sets = 2,
+        )),
+        fullAddressBits = ADDR_WIDTH,
+        banks = 1,
+        ways = 2,
+        sets = 2
+      )
+    })))
+
     l2_nodes.zipWithIndex.foreach { case (l2, i) =>
-      l3.module.io.rn(i) <> l2.module.io_chi
+      val chilogger = CHILogger(s"L3_L2[${i}]", true)
+      chilogger.io.up <> l2.module.io_chi
+      l3.io.rn(i) <> chilogger.io.down
       dontTouch(l2.module.io)
 
       l2.module.io.hartId := i.U
       l2.module.io_nodeID := i.U(NODEID_WIDTH.W)
       l2.module.io.debugTopDown := DontCare
       l2.module.io.l2_tlb_req <> DontCare
     }
+
+    val chilogger = CHILogger(s"MEM_L3", true)
+    l3.io.sn.connect(chilogger.io.up)
+    l3Bridge.module.io.chi.connect(chilogger.io.down)
+    l3.io.nodeID := numCores.U(NODEID_WIDTH.W)
   }
 }