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aws2.0 #103

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bfba99d
add dma support through pcie
grigoriy-chirkov Oct 2, 2019
d921c19
add virtual devices
grigoriy-chirkov Oct 2, 2019
68e318b
add PCIe DMA and config options for xupp3r
grigoriy-chirkov Nov 4, 2019
7b598b1
Merge branch 'openpiton-dev' of github.com:grigoriy-chirkov/openpiton…
grigoriy-chirkov Nov 4, 2019
fa154b8
Cleared out mc_top.v, merged DMA infrastructure for XUPP3R and F1
grigoriy-chirkov Feb 3, 2020
601b1e7
revert xilinx IP to 2016.4 versions
grigoriy-chirkov Feb 3, 2020
a41cd1d
update fifo IPs on vu9p boards
grigoriy-chirkov Feb 4, 2020
1c5ee34
removed aws submodule
grigoriy-chirkov Feb 4, 2020
a31249a
copy f1 files and scripts into main repo
grigoriy-chirkov Feb 6, 2020
c1967e8
fix f1 synthesis
grigoriy-chirkov Feb 6, 2020
0412e66
fix protosyn f1 flow
grigoriy-chirkov Feb 6, 2020
0721518
add option for second uart (works with ariane only)
grigoriy-chirkov Feb 6, 2020
448ce7e
fix typos
grigoriy-chirkov Feb 7, 2020
fb6c08a
add aws clocks to gitignore
grigoriy-chirkov Feb 7, 2020
93967e2
dma_os utility for pci enabled boards
grigoriy-chirkov Feb 11, 2020
3d26996
migrate uart script to openpiton repo
grigoriy-chirkov Feb 11, 2020
4fdf666
unified script for reset
grigoriy-chirkov Feb 11, 2020
add572c
enable reset script for pci boards
grigoriy-chirkov Feb 11, 2020
5b69264
fix confusing DDR3 defines
grigoriy-chirkov Feb 11, 2020
e7e04ae
sudo privileges for xdma scripts
grigoriy-chirkov Feb 11, 2020
007abb9
fix license headers
Feb 12, 2020
3ff2c52
off scripts
grigoriy-chirkov Feb 12, 2020
d24053c
built-in reversing of bytes in dma_os
grigoriy-chirkov Feb 12, 2020
c1361ba
raise freq to 100 MHz on xupp3r
grigoriy-chirkov Feb 6, 2020
141f560
add usage printout in dma_os
grigoriy-chirkov Feb 13, 2020
ea3c988
interrupts in chipset_impl are now taken from devices.xml
grigoriy-chirkov Feb 15, 2020
7bfadcf
add ariane debug via jtag on f1
grigoriy-chirkov Jun 10, 2021
be64e6d
add f1 utilities binaries to .gitignore
grigoriy-chirkov Jun 10, 2021
919e631
Merge branch 'openpiton-dev' of github.com:PrincetonUniversity/openpi…
grigoriy-chirkov Jun 11, 2021
bdd5193
fix python2 code in virtual_dev_translator.v.pyv
grigoriy-chirkov Jun 15, 2021
6a4ba69
simplify resets/switches/leds in piton_aws top module
grigoriy-chirkov Jun 15, 2021
22d350d
fixes for sparc core
grigoriy-chirkov Jun 17, 2021
98e0426
remove ila leftover
grigoriy-chirkov Jun 17, 2021
8cff78b
fix packet ordering to/from memory in noc_axi4_bridge
grigoriy-chirkov Jun 17, 2021
607c376
ariane jtag doesnt work on f1, remove for now
grigoriy-chirkov Jun 18, 2021
5ee37e0
fix for uart2 (now works)
grigoriy-chirkov Jun 20, 2021
ba7cd83
fix license headers
grigoriy-chirkov Jun 23, 2021
02bfa22
modified readme section about f1
grigoriy-chirkov Jun 23, 2021
94a736f
fix in axi4_bridge_ser
grigoriy-chirkov Oct 21, 2021
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add PCIe DMA and config options for xupp3r
  • Loading branch information
grigoriy-chirkov committed Nov 4, 2019
commit 68e318b8a703918b7938c145b9cee31374be632f
52 changes: 52 additions & 0 deletions piton/design/chipset/include/axi_defines.vh
Original file line number Diff line number Diff line change
@@ -0,0 +1,52 @@
// ========== Copyright Header Begin ============================================
// Copyright (c) 2019 Princeton University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of Princeton University nor the
// names of its contributors may be used to endorse or promote products
// derived from this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY PRINCETON UNIVERSITY "AS IS" AND
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
// DISCLAIMED. IN NO EVENT SHALL PRINCETON UNIVERSITY BE LIABLE FOR ANY
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ========== Copyright Header End ============================================

`ifndef AXI_DEFINES_VH
`define AXI_DEFINES_VH


`define AXI4_DATA_WIDTH 512
`define AXI4_ID_WIDTH 16
`define AXI4_ADDR_WIDTH 64
`define AXI4_LEN_WIDTH 8
`define AXI4_SIZE_WIDTH 3
`define AXI4_STRB_WIDTH 64
`define AXI4_BURST_WIDTH 2
`define AXI4_RESP_WIDTH 2
`define AXI4_CACHE_WIDTH 4
`define AXI4_PROT_WIDTH 3
`define AXI4_QOS_WIDTH 4
`define AXI4_REGION_WIDTH 4
`define AXI4_USER_WIDTH 11

`define AXIL_ADDR_WIDTH 32
`define AXIL_PROT_WIDTH 3
`define AXIL_DATA_WIDTH 32
`define AXIL_STRB_WIDTH 4
`define AXIL_RESP_WIDTH 2

`endif
2 changes: 1 addition & 1 deletion piton/design/chipset/include/mc_define.h
Original file line number Diff line number Diff line change
@@ -68,7 +68,7 @@
`define DDR3_BG_WIDTH 1
`define DDR3_ODT_WIDTH 1
`elsif XUPP3R_BOARD
`define BOARD_MEM_SIZE_MB 32768
`define BOARD_MEM_SIZE_MB 16384
`define WORDS_PER_BURST 8
`define WORD_SIZE 8 // in bytes
`define MIG_APP_ADDR_WIDTH 32
266 changes: 105 additions & 161 deletions piton/design/chipset/mc/rtl/mc_top.v

Large diffs are not rendered by default.

57 changes: 36 additions & 21 deletions piton/design/chipset/noc_axi4_bridge/rtl/axi4_zeroer.v
Original file line number Diff line number Diff line change
@@ -138,39 +138,54 @@ module axi4_zeroer (
localparam reg [63:0] BOARD_MEM_SIZE_MB = `BOARD_MEM_SIZE_MB;
localparam reg [`AXI4_ADDR_WIDTH-1:0] MAX_MEM_ADDR = (BOARD_MEM_SIZE_MB * 2**20);
localparam REQUESTS_NEEDED = MAX_MEM_ADDR / `AXI4_STRB_WIDTH; // basically max addr divided by size of one request
localparam MAX_OUTSTANDING = 16;

wire zeroer_req_val;
wire zeroer_resp_rdy;
wire req_go;
wire resp_go;
reg [`AXI4_ADDR_WIDTH-1:0] req_sent;
reg [`AXI4_ADDR_WIDTH-1:0] resp_got;
reg [3:0] outstanding;
wire [`AXI4_ADDR_WIDTH-1:0] zeroer_addr;
wire zeroer_wlast;

wire zeroer_addr_val = init_calib_complete_in & (waddr_req_sent < REQUESTS_NEEDED);
wire zeroer_data_val = init_calib_complete_in & (wdata_req_sent < REQUESTS_NEEDED);
wire zeroer_resp_rdy = init_calib_complete_in & (resp_got < REQUESTS_NEEDED);
assign zeroer_req_val = init_calib_complete_in
& (req_sent < REQUESTS_NEEDED)
& (outstanding != MAX_OUTSTANDING-1)
& m_axi_awready
& m_axi_wready
& rst_n;

wire waddr_req_go = zeroer_addr_val & m_axi_awready;
wire wdata_req_go = zeroer_data_val & m_axi_wready;
wire resp_go = zeroer_resp_rdy & m_axi_bvalid;
assign zeroer_resp_rdy = init_calib_complete_in
& (resp_got < REQUESTS_NEEDED)
& rst_n;

assign req_go = zeroer_req_val;
assign resp_go = zeroer_resp_rdy & m_axi_bvalid;

reg [`AXI4_ADDR_WIDTH-1:0] waddr_req_sent;
reg [`AXI4_ADDR_WIDTH-1:0] wdata_req_sent;
reg [`AXI4_ADDR_WIDTH-1:0] resp_got;

always @(posedge clk) begin
if(~rst_n) begin
waddr_req_sent <= 0;
wdata_req_sent <= 0;
req_sent <= 0;
resp_got <= 0;
outstanding <= 0;
end
else begin
waddr_req_sent <= waddr_req_sent + waddr_req_go;
wdata_req_sent <= wdata_req_sent + wdata_req_go;
req_sent <= req_sent + req_go;
resp_got <= resp_got + resp_go;
outstanding <= req_go & resp_go ? outstanding
: req_go ? outstanding + 1
: resp_go ? outstanding - 1
: outstanding;
end
end

as#it_calib_complete_out = (waddr_req_sent == REQUESTS_NEEDED) &
(wdata_req_sent == REQUESTS_NEEDED) &
(resp_got == REQUESTS_NEEDED);

wire [`AXI4_ADDR_WIDTH-1:0] zeroer_addr = waddr_req_sent * `AXI4_STRB_WIDTH;
as#it_calib_complete_out = (req_sent == REQUESTS_NEEDED) &
(resp_got == REQUESTS_NEEDED);

assign zeroer_addr = req_sent * `AXI4_STRB_WIDTH;
assign zeroer_wlast = zeroer_req_val;

always @(*) begin
if (~init_calib_complete_out) begin
@@ -185,14 +200,14 @@ always @(*) begin
m_axi_awqos = `AXI4_QOS_WIDTH'b0;
m_axi_awregion = `AXI4_REGION_WIDTH'b0;
m_axi_awuser = `AXI4_USER_WIDTH'b0;
m_axi_awvalid = zeroer_addr_val;
m_axi_awvalid = zeroer_req_val;

m_axi_wid = `AXI4_ID_WIDTH'b0;
m_axi_wdata = {`AXI4_DATA_WIDTH{1'b0}};
m_axi_wstrb = {`AXI4_STRB_WIDTH{1'b1}};
m_axi_wlast = 1'b1;
m_axi_wlast = zeroer_wlast;
m_axi_wuser = `AXI4_USER_WIDTH'b0;
m_axi_wvalid = zeroer_data_val;
m_axi_wvalid = zeroer_req_val;

m_axi_arid = `AXI4_ID_WIDTH'b0;
m_axi_araddr = `AXI4_ADDR_WIDTH'b0;
Original file line number Diff line number Diff line change
@@ -78,9 +78,9 @@ localparam READ = 1'd0;
localparam WRITE = 1'd1;


reg pkt_state_buf [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0];
reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_state_buf ;
reg [`MSG_HEADER_WIDTH-1:0] pkt_header[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0];
reg pkt_command[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0];
reg [`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0] pkt_command;

reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_in;
reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] fifo_out;
@@ -101,6 +101,7 @@ wire write_req_go = (write_req_val & write_req_rdy);
wire write_resp_go = (write_resp_val & write_resp_rdy);
wire req_go = read_req_go || write_req_go;
wire preser_rdy = ~ser_val_ff || ser_rdy;
wire ser_go = ser_val & ser_rdy;

//
// SEND REQUESTS
@@ -131,7 +132,8 @@ generate
if ((i == fifo_in) & deser_go) begin
pkt_state_buf[i] <= WAITING;
pkt_header[i] <= deser_header;
pkt_command[i] <= (deser_header[`MSG_TYPE] == `MSG_TYPE_STORE_MEM);
pkt_command[i] <= (deser_header[`MSG_TYPE] == `MSG_TYPE_STORE_MEM)
|| (deser_header[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ);
end
else if ((i == fifo_out) & req_go) begin
pkt_state_buf[i] <= INVALID;
@@ -140,7 +142,7 @@ generate
end
else begin
pkt_state_buf[i] <= pkt_state_buf[i];
pkt_header[i] <= pkt_header[i];
pkt_header[i] <= pkt_header[i];
pkt_command[i] <= pkt_command[i];
end
end
17 changes: 2 additions & 15 deletions piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_define.vh
Original file line number Diff line number Diff line change
@@ -1,4 +1,3 @@

// ========== Copyright Header Begin ============================================
// Copyright (c) 2019 Princeton University
// All rights reserved.
@@ -26,20 +25,8 @@
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ========== Copyright Header End ============================================

`include "axi_defines.vh"

`define NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT 16
`define NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE 4 //log(NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT)


`define AXI4_DATA_WIDTH 512
`define AXI4_ID_WIDTH 16
`define AXI4_ADDR_WIDTH 64
`define AXI4_LEN_WIDTH 8
`define AXI4_SIZE_WIDTH 3
`define AXI4_STRB_WIDTH 64
`define AXI4_BURST_WIDTH 2
`define AXI4_RESP_WIDTH 2
`define AXI4_CACHE_WIDTH 4
`define AXI4_PROT_WIDTH 3
`define AXI4_QOS_WIDTH 4
`define AXI4_REGION_WIDTH 4
`define AXI4_USER_WIDTH 11
13 changes: 9 additions & 4 deletions piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_read.v
Original file line number Diff line number Diff line change
@@ -88,7 +88,7 @@ wire [`AXI4_ADDR_WIDTH-1:0]addr_paddings = `AXI4_ADDR_WIDTH'b0;
assign m_axi_arburst = `AXI4_BURST_WIDTH'b01; // fixed address in bursts (doesn't matter cause we use length-1 bursts)
assign m_axi_arlock = 1'b0; // Do not use locks
assign m_axi_arcache = `AXI4_CACHE_WIDTH'b11; // Non-cacheable bufferable requests
assign m_axi_arprot = `AXI4_PROT_WIDTH'b10; // Data access, non-secure access, unpriveleged access
assign m_axi_arprot = `AXI4_PROT_WIDTH'b0; // Data access, non-secure access, unpriveleged access
assign m_axi_arqos = `AXI4_QOS_WIDTH'b0; // Do not use qos
assign m_axi_arregion = `AXI4_REGION_WIDTH'b0; // Do not use regions
assign m_axi_aruser = `AXI4_USER_WIDTH'b0; // Do not use user field
@@ -133,7 +133,7 @@ end


// Process information here
assign m_axi_arid = req_id_f;
assign m_axi_arid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f};

wire [`PHY_ADDR_WIDTH-1:0] virt_addr = req_header_f[`MSG_ADDR];
wire [`AXI4_ADDR_WIDTH-1:0] phys_addr;
@@ -156,7 +156,8 @@ reg [6:0] size[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0];
reg [5:0] offset[`NOC_AXI4_BRIDGE_IN_FLIGHT_LIMIT-1:0];
reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] resp_id_f;
wire resp_go;
wire uncacheable = (virt_addr[`PHY_ADDR_WIDTH-1]);
wire sd_card = (virt_addr[`PHY_ADDR_WIDTH-1]);
wire uncacheable = (req_header_f[`MSG_TYPE] == `MSG_TYPE_NC_LOAD_REQ);

generate begin
genvar i;
@@ -168,7 +169,11 @@ generate begin
end
else begin
if ((i == req_id_f) && m_axi_argo) begin
if (uncacheable) begin
if (sd_card) begin
offset[i] <= {virt_addr[5:3], 3'b0};
size[i] <= 7'd8;
end
else if (uncacheable) begin
offset[i] <= virt_addr[5:0];
case (req_header_f[`MSG_DATA_SIZE])
`MSG_DATA_SIZE_0B: begin
Original file line number Diff line number Diff line change
@@ -142,6 +142,14 @@ always @(posedge clk) begin
resp_header[`MSG_TYPE ] <= `MSG_TYPE_STORE_MEM_ACK;
resp_header[`MSG_LENGTH ] <= 0;
end
`MSG_TYPE_NC_LOAD_REQ: begin
resp_header[`MSG_TYPE ] <= `MSG_TYPE_NC_LOAD_MEM_ACK;
resp_header[`MSG_LENGTH ] <= `PAYLOAD_LEN;
end
`MSG_TYPE_NC_STORE_REQ: begin
resp_header[`MSG_TYPE ] <= `MSG_TYPE_NC_STORE_MEM_ACK;
resp_header[`MSG_LENGTH ] <= 0;
end
default: begin
// shouldn't end up herere
resp_header[`MSG_TYPE ] <= `MSG_TYPE_WIDTH'b0;
28 changes: 17 additions & 11 deletions piton/design/chipset/noc_axi4_bridge/rtl/noc_axi4_bridge_write.v
Original file line number Diff line number Diff line change
@@ -94,7 +94,7 @@ localparam GOT_RESP = 3'd1;
assign m_axi_awburst = `AXI4_BURST_WIDTH'b01; // fixed address in bursts (doesn't matter cause we use length-1 bursts)
assign m_axi_awlock = 1'b0; // Do not use locks
assign m_axi_awcache = `AXI4_CACHE_WIDTH'b11; // Non-cacheable bufferable requests
assign m_axi_awprot = `AXI4_PROT_WIDTH'b10; // Data access, non-secure access, unpriveleged access
assign m_axi_awprot = `AXI4_PROT_WIDTH'b0; // Data access, non-secure access, unpriveleged access
assign m_axi_awqos = `AXI4_QOS_WIDTH'b0; // Do not use qos
assign m_axi_awregion = `AXI4_REGION_WIDTH'b0; // Do not use regions
assign m_axi_awuser = `AXI4_USER_WIDTH'b0; // Do not use user field
@@ -106,16 +106,16 @@ wire [`AXI4_ADDR_WIDTH-1:0] addr_paddings = `AXI4_ADDR_WIDTH'b0;
wire m_axi_awgo = m_axi_awvalid & m_axi_awready;
wire m_axi_wgo = m_axi_wvalid & m_axi_wready;
wire req_go = req_val & req_rdy;
assign m_axi_wlast = m_axi_wgo;
assign m_axi_wlast = m_axi_wvalid;

reg [2:0] req_state;
reg [`MSG_HEADER_WIDTH-1:0] req_header_f;
reg [`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE-1:0] req_id_f;
reg [`AXI4_DATA_WIDTH-1:0] req_data_f;

assign req_rdy = (req_state == IDLE);
assign m_axi_awvalid = (req_state == PREP_REQ);
assign m_axi_wvalid = (req_state == PREP_REQ);
assign m_axi_awvalid = (req_state == PREP_REQ) || (req_state == SENT_W);
assign m_axi_wvalid = (req_state == PREP_REQ) || (req_state == SENT_AW);

always @(posedge clk) begin
if(~rst_n) begin
@@ -151,8 +151,8 @@ always @(posedge clk) begin
end
SENT_W: begin
req_state <= m_axi_awgo ? IDLE : req_state;
req_header_f <= m_axi_awgo ? IDLE : req_header_f;
req_id_f <= m_axi_awgo ? IDLE : req_id_f;
req_header_f <= m_axi_awgo ? 0 : req_header_f;
req_id_f <= m_axi_awgo ? 0 : req_id_f;
req_data_f <= m_axi_awgo ? 0 : req_data_f;
end
default : begin
@@ -167,13 +167,14 @@ end


// Process information here
assign m_axi_awid = req_id_f;
assign m_axi_wid = req_id_f;
assign m_axi_awid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f};
assign m_axi_wid = {{`AXI4_ID_WIDTH-`NOC_AXI4_BRIDGE_BUFFER_ADDR_SIZE{1'b0}}, req_id_f};


wire [`PHY_ADDR_WIDTH-1:0] virt_addr = req_header_f[`MSG_ADDR];
wire [`AXI4_ADDR_WIDTH-1:0] phys_addr;
wire uncacheable = (virt_addr[`PHY_ADDR_WIDTH-1]);
wire sd_card = (virt_addr[`PHY_ADDR_WIDTH-1]);
wire uncacheable = (req_header_f[`MSG_TYPE] == `MSG_TYPE_NC_STORE_REQ);

// If running uart tests - we need to do address translation
`ifdef PITONSYS_UART_BOOT
@@ -197,7 +198,10 @@ always @(posedge clk) begin
addr <= `AXI4_ADDR_WIDTH'b0;
end
else begin
if (uncacheable) begin
if (sd_card) begin
strb_before_offset <= `AXI4_STRB_WIDTH'hff;
end
else if (uncacheable) begin
case (req_header_f[`MSG_DATA_SIZE])
`MSG_DATA_SIZE_0B: begin
strb_before_offset <= `AXI4_STRB_WIDTH'b0;
@@ -233,7 +237,9 @@ always @(posedge clk) begin
strb_before_offset <= `AXI4_STRB_WIDTH'hffffffffffffffff;
end

offset <= uncacheable ? virt_addr[5:0] : 6'b0;
offset <= uncacheable ? virt_addr[5:0]
: sd_card ? {virt_addr[5:3], 3'b0}
: 6'b0;
addr <= uart_boot_en ? {phys_addr[`AXI4_ADDR_WIDTH-4:0], 3'b0} : virt_addr;
end
end
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