Fix declassign regs #136
Open
Fix declassign regs #136
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
in verilog, the statement ``` reg my_reg = 0; ``` is the same as ``` reg my_reg; initial my_reg = 0; ``` whereas in the current HEAD, the statement above is translated to ``` reg my_reg; assign my_reg = 0; ``` This commit fixes this bug
# for free
to join this conversation on GitHub.
Already have an account?
# to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Problem:
In Verilog, the statement
is the same as
whereas in the current HEAD, the statement above
is translated to
Solution
This commit fixes this bug by converting the assignment ast node to a blocking assignment wrapped in an initial block.