Fix UnitarySynthesis for 3+ qubits when compiled for a backend (backport #13591)

[mergify]

Summary

When encountering a 3+ qubit UnitaryGate, UnitarySynthesis currently replaces the whole dag with the definition of the block instead of appending it, see

qiskit/crates/accelerate/src/unitary_synthesis.rs

Line 375 in 079f69f

out_dag = synth_dag;

Details and comments

This also leads to #13586 because the qubit/clbit interners are overwritten, but maybe more importantly this can lead to issues when multiple 3-qubit blocks are present in the circuit. E.g. running

import numpy as np
from qiskit.quantum_info import Operator
from qiskit.circuit.library import UnitaryGate
from qiskit import QuantumCircuit, transpile
from qiskit_ibm_runtime.fake_provider import FakeSherbrooke

backend = FakeSherbrooke()

x = QuantumCircuit(3)
x.x(2)
x_mat = Operator(x)

qc = QuantumCircuit(3, 1)
qc.unitary(x_mat, range(3))
qc.unitary(np.eye(2 ** 3), range(3))

tqc = transpile(qc, backend, optimization_level=0)
print(tqc.count_ops())

produces an empty circuit, since the last block implements the identity.

Some additional tests, such as the precise case of #13586 and a series of 3q UnitaryGates, should be added.

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This is an automatic backport of pull request #13591 done by [Mergify](https://mergify.com).

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[coveralls]

Pull Request Test Coverage Report for Build 12652064901

Details

• 2 of 2 (100.0%) changed or added relevant lines in 1 file are covered.
• 4 unchanged lines in 2 files lost coverage.
• Overall coverage increased (+0.02%) to 88.947%

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Files with Coverage Reduction	New Missed Lines	%
crates/accelerate/src/unitary_synthesis.rs	1	93.18%
crates/qasm2/src/lex.rs	3	92.73%

Totals
Change from base Build 12631844630:	0.02%
Covered Lines:	79149
Relevant Lines:	88984

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💛 - Coveralls