[WIP] Bits and Registers #13860
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[WIP] Bits and Registers #13860
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Co-authored-by: Jake Lishman <jake.lishman@ibm.com>
- Use `macro_rules!` to create `Bit` and `Registers`.
- Add `new_owned` method for `BitInfo`.
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- Rebalance currently available api to allow for superclasses `Bit` and `Register` to also live in Rust. - Remove: `ShareableBit` triat and structs that implement it. Replace them with new structs.
- Add prefix class attribute for python `Register` instances.
- Add `BitExtraInfo` as a soft identifier for `BitInfo`, can be null to identify a `Bit`. - Add `RegisterInfo::get` method to retrieve the information of a `Bit`. - Have the rust registers own their counters instead of having them be Python exclusive. - Make subclassing of `Regster` and `Bit` a bit more effective by helping the subclasses inherit most methods.
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…GCircuit`. - Modify `BitData` to accept an extra generic value specifying a "sharable" object type that can also be turned into a `PyObject` to allow for compatibility with `Var`. - Rename `BitAsKey` to `VarAsKey` as it is currently only used for `Var` instances. - Modify methods in `CommutationChecker` and `GateDirection` passes to use the newer methods. - Other tweaks and fixes.
…bit`. - Remove imports of `QUBIT` and `CLBIT` from `DAGCircuit` and `CircuitData`.
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Summary
Bits and registers in Rust (Part 2)
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