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  • Saint Petersburg State University of Telecommunications
  • Saint Petersburg, Russia

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  1. verilog-transceiver Public

    Educational project for the Xilinx ZedBoard Zynq-7000 Development Kit

    Verilog 3 2

  2. axis-i2c-master Public

    AXI-Stream I2C Master module

    SystemVerilog 2

  3. fpga-useful-list Public

    List of useful materials on FPGA topic

    3

  4. si5340-config-loader Public

    Module for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface

    Verilog 1

  5. schoolRISCV Public

    Forked from zhelnio/schoolRISCV

    CPU microarchitecture, step by step

    Makefile

  6. axis-uart Public

    AXI-Stream UART module

    SystemVerilog

844 contributions in the last year

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Contribution activity

February 2025

Created 1 repository
  • RDSik/axis-uart SystemVerilog
    This contribution was made on Feb 15
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