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Saint Petersburg State University of Telecommunications
- Saint Petersburg, Russia
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verilog-transceiver
verilog-transceiver PublicEducational project for the Xilinx ZedBoard Zynq-7000 Development Kit
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si5340-config-loader
si5340-config-loader PublicModule for load configuration from ClockBuilderPro to Si5340 PLL via i2c interface
Verilog 1
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schoolRISCV
schoolRISCV PublicForked from zhelnio/schoolRISCV
CPU microarchitecture, step by step
Makefile
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844 contributions in the last year
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Contribution activity
February 2025
Created 53 commits in 3 repositories
Created 1 repository
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RDSik/axis-uart
SystemVerilog
This contribution was made on Feb 15