SM8550: Odin 2 use downstream sdhci driver

ROCKNIX · Feb 26, 2025 · 880a414 · 880a414
1 parent 129c929
commit 880a414
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Showing 3 changed files with 6,282 additions and 2 deletions.
diff --git a/projects/Qualcomm/devices/SM8550/linux/linux.aarch64.conf b/projects/Qualcomm/devices/SM8550/linux/linux.aarch64.conf
@@ -5381,6 +5381,7 @@ CONFIG_MMC_SDHCI_PLTFM=y
 # CONFIG_MMC_SDHCI_F_SDH30 is not set
 # CONFIG_MMC_SDHCI_MILBEAUT is not set
 CONFIG_MMC_SDHCI_MSM=y
+CONFIG_MMC_SDHCI_MSM_DOWNSTREAM=y
 # CONFIG_MMC_TIFM_SD is not set
 CONFIG_MMC_SPI=y
 # CONFIG_MMC_CB710 is not set

diff --git a/projects/Qualcomm/patches/linux/SM8550/0050_arm64--dts--qcom--Add-AYN-Odin2-Pro.patch b/projects/Qualcomm/patches/linux/SM8550/0050_arm64--dts--qcom--Add-AYN-Odin2-Pro.patch
@@ -1,7 +1,7 @@
 diff -rupbN linux.orig/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts linux/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts
 --- linux.orig/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts	1970-01-01 00:00:00.000000000 +0000
-+++ linux/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts	2025-02-25 14:19:17.327428808 +0000
-@@ -0,0 +1,141 @@
++++ linux/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts	2025-02-26 02:32:30.675906248 +0000
+@@ -0,0 +1,237 @@
 +// SPDX-License-Identifier: BSD-3-Clause
 +/*
 + * Copyright (c) 2025, Teguh Sobirin.
@@ -143,3 +143,99 @@ diff -rupbN linux.orig/arch/arm64/boot/dts/qcom/qcs8550-ayn-odin2pro.dts linux/a
 +&spk_amp_r {
 +	firmware-name = "qcom/sm8550/ayn/odin2portal/aw883xx_acf.bin";
 +};
++
++&soc {
++    qcom_tzlog: qcom_tzlog {
++        status = "disabled";
++    };
++
++    arch_timer: arch_timer {
++        status = "disabled";
++    };
++};
++
++/delete-node/ &sdhc_2;
++
++&soc {
++	sdhc_2: sdhci@8804000 {
++		compatible = "qcom,sdhci-msm-v5-downstream";
++		reg = <0 0x08804000 0 0x1000>;
++		reg-names = "hc_mem";
++		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
++					<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "hc_irq", "pwr_irq";
++		bus-width = <4>;
++		no-sdio;
++		no-mmc;
++		qcom,restore-after-cx-collapse;
++		qcom,uses_level_shifter;
++		qcom,dll_lock_bist_fail_wa;
++		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
++			<&gcc GCC_SDCC2_APPS_CLK>;
++		clock-names = "iface", "core";
++
++		/*
++		 * DLL HSR settings. Refer go/hsr - <Target> DLL settings.
++		 * Note that the DLL_CONFIG_2 value is not passed from the
++		 * device tree, but it is calculated in the driver.
++		 */
++		qcom,dll-hsr-list = <0x0007442C 0x0 0x10
++					0x090106C0 0x80040868>;
++
++		iommus = <&apps_smmu 0x540 0x0>;
++		dma-coherent;
++		interconnects = <&aggre2_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
++				<&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
++		interconnect-names = "sdhc-ddr", "cpu-sdhc";
++
++		qcom,msm-bus,name = "sdhc2";
++		qcom,msm-bus,num-cases = <0x07>;
++		qcom,msm-bus,num-paths = <0x02>;
++		qcom,msm-bus,vectors-KBps = <0x00 0x00 0x00 0x00 0x416 0xc80 0x640 0x640 0xff50 0x3d090 0x186a0 0x208c8 0x1fe9e 0x3d090 0x208c8 0x208c8 0x3fd3e 0x3d090 0x249f0 0x208c8 0x3fd3e 0xc3500 0x493e0 0x493e0 0x146cc2 0x3e8000 0x146cc2 0x3e8000>;
++		qcom,bus-bw-vectors-bps = <0x00 0x61a80 0x17d7840 0x2faf080 0x5f5e100 0xbebc200 0xffffffff>;
++
++		operating-points-v2 = <&sdhc2_opp_table>;
++
++		vdd-supply = <&vreg_l9b_2p9>;
++		qcom,vdd-voltage-level = <0x2d0370 0x2d2a80>;
++		qcom,vdd-current-level = <0x00 0xc3500>;
++
++		vdd-io-supply = <&vreg_l8b_1p8>;
++		qcom,vdd-io-voltage-level = <0x1b7740 0x2d2a80>;
++		qcom,vdd-io-current-level = <0x00 0x15e0>;
++
++		pinctrl-names = "default", "sleep";
++		pinctrl-0 = <&sdc2_default &sdc2_card_det_n>;
++		pinctrl-1 = <&sdc2_sleep &sdc2_card_det_n>;
++
++		cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>;
++		resets = <&gcc GCC_SDCC2_BCR>;
++		reset-names = "core_reset";
++
++		qos0 {
++			mask = <0xf0>;
++			vote = <0x2c>;
++		};
++
++		qos1 {
++			mask = <0x0f>;
++			vote = <0x2c>;
++		};
++
++		sdhc2_opp_table: opp-table {
++			compatible = "operating-points-v2";
++
++			opp-100000000 {
++				opp-hz = <0x00 0x5f5e100>;
++				opp-peak-kBps = <0x27100 0x186a0>;
++				opp-avg-kBps = <0xc350 0x00>;
++			};
++
++			opp-202000000 {
++				opp-hz = <0x00 0xc0a4680>;
++				opp-peak-kBps = <0x30d40 0x1d4c0>;
++				opp-avg-kBps = <0x19640 0x00>;
++			};
++		};
++	};
++};