STARS 2023 Design Final Project

SyntheSTARS

• Diego Jesus Lopez
• Emily Moreno
• Michael Foster
• Steph Close
• (TA) Aidan Prendergast

13-Channel Synthesizer

The (insert kewl chip name) is a digital polyphonic synthesizer. With thirteen keys each representative of a single note in a standard octave, a wave type selection mode, and an octave swithcing mode, the (insert kewl chip name) is the working product of our team's design.

Base Source Files

Clock and nRst omitted from input lists.

• keypad_encoder.sv : Synchronizer and Edge Detector Module. Routes to FSM and 13 Oscillators.
  • Inputs: [14:0] keypad_i
  • Outputs: [12:0] keypad_s, modekey_edge, octave_edge
• oscillator.sv : Parameterized oscillator module.
  • Parameter: DIVIDER (16-bit)
  • Inputs: enable, [1:0] octave
  • Outputs: [17:0] count
• sample_rate_clock_divider.sv : Sample Rate Clock Divider module.
  • Inputs: enable
  • Outputs: flag
• sequential_divider.sv : Sequential Divider module.
  • Inputs: enable, [15:0] divider, [17:0] count, flag
  • Outputs: [7:0] quotient
• waveshaper.sv : Wave shaping and enveloping module.
  • Inputs: [7:0] quotient, [1:0] mode
  • Outputs: [7:0] sample
• mixer.sv : Polyphonic wave mixer with sequential divider.
  • Inputs: enable, [12:0] [7:0] samples, [12:0] samples_enabled
  • Outputs: [7:0] sample_mixed
• pwm.sv : Pulse Width Modulation module.
  • Inputs: enable, [7:0] sample_mixed
  • Outputs: pwm_o (add pwm_o_n for differential pair?)
• wavetype_set_fsm.sv : Wave Mode Controller FSM module.
  • Inputs: modekey_edge
  • Outputs: [1:0] mode
• octave_fsm.sv : Octave switching FSM module.
  • Inputs: oct_down
  • Outputs: [1:0] oct_switch
• edge_dectector.sv : Edge detection pulse module.
  • Inputs: in
  • Outputs: out

Testbenching

• tb_base.sv : Base test bench template for further adaptation.
• tb_pwm.sv : Test bench for the pulse width modifier.
• tb_sequential_divider.sv : Test bench for the sequential divider.

Pin Layout

• GPIO (IN) 0-12: Note Pins (C4 to C5)
• GPIO (IN) 13: Mode Selector
• GPIO (IN) 14: Octave Selector
• GPIO (OUT) 15: PWM Output
• GPIO (NC) 16-33: Not Connected

Supporting Equipment

• Testing FPGA Prototype
• Audio Amplifier
• Low Pass Filter
• Speaker

RTL Diagrams

All the stuff from the proposal goes here, obviously updated from the time you did the proposal to the final layout Include more than just block diagrams, including sub-block diagrams, state-transition diagrams, flowcharts, and timing diagrams

Top level RTL: Full Chip Design

Module RTL: Wave Shaper

Module RTL: Keypad Encoder

Module RTL: Oscillator

Module RTL: Sample Rate Clock Divider

Module RTL: Pulse Width Modulater

Module RTL: Mixer

State Machine: Wave Type Selection FSM

State Machine: Octave Step-Down FSM

Most Recent Timing Diagram (I/O Pulses)

High Level Flowchart

Extensions

Add possible extensions here...

Deadlines and Events

Monday June 19th: Design Review Presentations

Present top-level and block-level diagrams to explain design function and timing behavior.
Requirements: Heirarchical RTL Diagrams, State Transition Diagrams, Flowcharts, Pseudocode in RTL, WaveDROM for timing specific blocks.
Notes: Share the presentation with instructors in advance.

Friday, June 23rd: Feature Freeze and Integration Mark

Complete individual blocks to the level of error-free synthesis and passing testbenches. Begin top level module creation, integration, and testing.
Requirements: Transcript of Passing Testbench Cases for each tested module, Organized GTKWave showcase of passing test cases.
Notes: Beautify GTKWave formatting for ease of demonstration.

Wednesday - Friday, July 5th - 7th: Final Design Presentations