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Is your feature request related to a problem? Please describe.
I use a lot Teros HDL for its linting and checking features in my VHDL projects. But, I face issues with IPs (or blackboxes). For example, when I try to import a Xilinx library teros reports "not found".
Describe the solution you'd like
Since the source code of IPs may not be available, it would be nice to have the option to mark something as a "blackbox" or ask Teros to ignore it simply. This feature may help to drop many false errors.
Describe alternatives you've considered
Support "blackboxes"
Ignore libraries and Verilog modules / VHDL entities, packages, functions and so on
The text was updated successfully, but these errors were encountered:
Is your feature request related to a problem? Please describe.
I use a lot Teros HDL for its linting and checking features in my VHDL projects. But, I face issues with IPs (or blackboxes). For example, when I try to import a Xilinx library teros reports "not found".
Describe the solution you'd like
Since the source code of IPs may not be available, it would be nice to have the option to mark something as a "blackbox" or ask Teros to ignore it simply. This feature may help to drop many false errors.
Describe alternatives you've considered
The text was updated successfully, but these errors were encountered: