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190 Open 282 Closed
190 Open 282 Closed
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Issues list

Vivado version not detected correctly when verifying the setup bug Something isn't working
#701 opened Nov 11, 2024 by fuzesa
1
[FIX] GHDL+Yosys Schematic Viewer Temporary File Spam Fix enhancement New feature or request
#700 opened Nov 9, 2024 by irshbn
1
Verify Setup issue bug Something isn't working
#697 opened Nov 8, 2024 by victobui
@keepports doesnt work bug Something isn't working
#695 opened Nov 5, 2024 by monkey265
Cannot run test benches for Verilog / render schematic views
#693 opened Nov 2, 2024 by washburn961
1
Add option to support "blackboxes" and ignore libraries enhancement New feature or request
#688 opened Oct 23, 2024 by rameloni
VHDL modules using Verilog libraries - library not found
#687 opened Oct 23, 2024 by rameloni
6
Recommended flow for standalone CLI documenter?
#685 opened Oct 15, 2024 by davidgussler
Snippet suggestions appear twice when using TerosHDL with VHDL-LS extension bug Something isn't working
#683 opened Oct 13, 2024 by davidgussler
Why my code doesn't produce a FSM ? bug Something isn't working
#682 opened Oct 6, 2024 by FinnNGrace
Issues in the configuration enhancement New feature or request
#680 opened Oct 3, 2024 by ecstrema
Indentation following vhdl 'when' clause bug Something isn't working
#678 opened Oct 2, 2024 by SittingDuc
3
Failed to access library 'C:\Users\namhe\.teroshdl_fryIl_' at "C:\Users\namhe\.teroshdl_fryIl_".TerosHDL: modelsim(vlog-19) bug Something isn't working
#677 opened Oct 1, 2024 by FinnNGrace
Quartus path resolution incorrect for windows, SILENT fallback to QUARTUS_ROOTDIR bug Something isn't working
#671 opened Sep 27, 2024 by dbee-novosound
3
Q: TerosHDL and Python virtual environments bug Something isn't working
#660 opened Sep 17, 2024 by mkaiser
3
Schematic viewer with GHDL/Yosys cannot find work lib bug Something isn't working
#659 opened Sep 14, 2024 by atticlabsdesign
2
Error when trying to instantiate an entity containing a generic type (VHDL 2008) bug Something isn't working
#658 opened Sep 10, 2024 by vdahle
VHDL comment type for Verilog testbench template bug Something isn't working
#656 opened Sep 5, 2024 by SebekO
Support for inline if statement in state machine viewer enhancement New feature or request
#655 opened Sep 5, 2024 by SebekO
Format selection (VHDL, possibly other languages as well) enhancement New feature or request
#653 opened Sep 4, 2024 by ckuhlmann
Add **Chinese** language support enhancement New feature or request
#643 opened Aug 21, 2024 by miilTgy
1
Support for specific VUnit project enhancement New feature or request
#641 opened Aug 15, 2024 by james-ziegler
5
[FEATURE REQUEST]: Update XDC language for more highlights enhancement New feature or request
#640 opened Aug 8, 2024 by wimille
1
Comment/Description for Last Signal Missing in Module documentation bug Something isn't working
#637 opened Jul 23, 2024 by jchang-endiag
VHDL 2008 Block Comment End Characters Appear in Documentation enhancement New feature or request
#636 opened Jul 23, 2024 by jchang-endiag
1
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