Updated unit tests.

VUnit · Sep 7, 2024 · 9c3524b · 9c3524b
1 parent 6bcd461
commit 9c3524b
Showing 1 changed file with 9 additions and 9 deletions.
diff --git a/tests/unit/test_modelsim_interface.py b/tests/unit/test_modelsim_interface.py
@@ -35,7 +35,7 @@ def test_compile_project_vhdl_2008(self, process, check_output):
         write_file("file.vhd", "")
         project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2008"))
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vcom"),
@@ -58,7 +58,7 @@ def test_compile_project_vhdl_2002(self, process, check_output):
         write_file("file.vhd", "")
         project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2002"))
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vcom"),
@@ -81,7 +81,7 @@ def test_compile_project_vhdl_93(self, process, check_output):
         write_file("file.vhd", "")
         project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("93"))
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vcom"),
@@ -105,7 +105,7 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output):
         source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
         source_file.set_compile_option("modelsim.vcom_flags", ["custom", "flags"])
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vcom"),
@@ -130,7 +130,7 @@ def test_compile_project_verilog(self, process, check_output):
         write_file("file.v", "")
         project.add_source_file("file.v", "lib", file_type="verilog")
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vlog"),
@@ -154,7 +154,7 @@ def test_compile_project_system_verilog(self, process, check_output):
         write_file("file.sv", "")
         project.add_source_file("file.sv", "lib", file_type="systemverilog")
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vlog"),
@@ -180,7 +180,7 @@ def test_compile_project_verilog_extra_flags(self, process, check_output):
         source_file = project.add_source_file("file.v", "lib", file_type="verilog")
         source_file.set_compile_option("modelsim.vlog_flags", ["custom", "flags"])
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vlog"),
@@ -206,7 +206,7 @@ def test_compile_project_verilog_include(self, process, check_output):
         write_file("file.v", "")
         project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         check_args = [
             str(Path(self.prefix_path) / "vlog"),
@@ -231,7 +231,7 @@ def test_compile_project_verilog_define(self, process, check_output):
         write_file("file.v", "")
         project.add_source_file("file.v", "lib", file_type="verilog", defines={"defname": "defval"})
         simif.compile_project(project)
-        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "lib_path"]
+        process_args = [str(Path(self.prefix_path) / "vlib"), "-unix", "-type", "directory", "lib_path"]
         process.assert_called_once_with(process_args, env=simif.get_env())
         process_args = [
             str(Path(self.prefix_path) / "vlog"),