This repository contains the deliverables and documentation for the Analog CMOS Final Project, where we design an LDO (Low Dropout Regulator) using the HP 45nm technology node. The project employs the gm/id methodology to generate technology-specific plots and design the LDO circuit.
In this project we have designed an LDO subject to different conditions. For this design we are designing the LDO for both externally and internally compensated LDO. We have considered different technology nodes and different legths for the same.Our aim is to design the LDO for a max and a min load condition and see where the outputs are more desireable.For additional details on the implementation, refer to the ACMOS_report.pdf. The sizing_sheets file provides the sizes of all FETs used in the circuits.
- Vadlamudi Karthikeya
- Rohit Mogli
- Yogesh Goyyal