How do I use synth_xilinx so that it passes -sv into read_verilog?

[slendidev]

	yosys -p "synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json" $< ${ADDITIONAL_SOURCES}

This is what I have

[nakengelhardt]

Read the sources explicitly:

	yosys -p "read_verilog -sv ${ADDITIONAL_SOURCES}; synth_xilinx -flatten -abc9 ${SYNTH_OPTS} -arch xc7 -top ${TOP_MODULE}; write_json ${PROJECT}.json"

If you put the file names on the command line, yosys will guess based on the file extension, so you could also rename all your files to use .sv extension.

[povik]

Also adding the -f 'verilog -sv' option on the command line should do what OP is asking for

[slendidev]

@povik's answer seems to be the simplest. Thank you both!